SOC Physical Design Engineer

General Summary

This individual leads the Physical Design Flow for high-speed DDR, graphics, and other SoC components, focusing on power utilization and optimization. The role synthesizes ambiguous or conflicting requirements and manages complex responsibilities across physical verification flows, micro‑architecture, SOC algorithm design and modeling, and methodology.

• Floor planning
• Clock tree synthesis
• Place and route
• Power delivery network (PDN)
• Timing analysis and closure
• Perform physical verification checks (LVS, DRC, design‑for‑manufacturing & design‑for‑yield) at chip and block levels
• Provide schedules and support cross‑functional engineering effort to drive signoff closure for tapeout
• Act as a strong contributor at design reviews and project meetings, communicating and implementing a development plan

Preferred educational background includes a Master’s Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related field with at least 3 years of experience in a related occupation; or a Bachelor’s Degree (or foreign academic equivalent) in the same fields with 7+ years of progressive experience. Employer will accept any suitable combination of education, training or experience.

$161,179 – $210,000 per year.

Qualcomm is an equal‑opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Qualcomm provides reasonable accommodations for individuals with disabilities during the application and hiring process. If you need an accommodation, please contact disability‑ or call the Qualcomm toll‑free number.

If you would like more information about this role, please contact Qualcomm Careers.