Distinguished Engineer, End-to-End Scaling Performance Architecture

We are looking for a Distinguished Engineer to join NVIDIA's architecture organization and help define how future accelerated computing systems scale from a single processor to multi-die, multi-GPU, and multi-node platforms! In this role, we will rely on you to set long-term performance strategy across applications, systems, and architecture, including DRAM, NVLink, and chip-to-chip (C2C) interconnects.

We focus this role on architectural direction and application outcomes. We need someone who can identify where data movement, communication, memory behavior, topology, and compute limit scaling, then turn those insights into priorities that guide multiple product generations. Our domain teams own detailed implementation and delivery. We will count on you to align their decisions around a shared end-to-end strategy so local improvements create meaningful system-level gains.

What You Will Be Doing:

Ask you to define the multi-generation strategy for application scaling across DRAM, NVLink, C2C, compute, and the supporting software stack.

Translate the behavior of important AI, HPC, and accelerated computing applications into architectural requirements, performance targets, and investment priorities.

Rely on you to build a clear view of how bottlenecks shift as workloads scale across dies, GPUs, nodes, model sizes, data sets, and communication patterns.

Evaluate system-level trade-offs across bandwidth, latency, capacity, topology, coherence, power, area, cost, programmability, and resiliency.

Use your leadership to establish common workload scenarios, scaling metrics, models, and decision frameworks so architecture teams can compare proposals against application outcomes.

Count on you to identify architectural discontinuities and emerging technology opportunities early enough to shape product and technology decisions. We will partner with you to align DRAM, NVLink, C2C, GPU, CPU, system, and software architects around shared performance limits and high-value opportunities. You will work with application, framework, compiler, runtime, modeling, and post-silicon teams to connect measured behavior with future architecture choices.

Value your clear recommendations to senior technical and business leaders, including assumptions, sensitivities, risks, and expected impact. We will also ask you to mentor system performance architects, strengthen technical communities across teams, generate sustained intellectual property, and help influence the direction of large-scale accelerated computing.

What We Need To SeeMSEE, MSCE, PhD, or equivalent experience in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
18+ years of relevant industry or academic experience, including experience setting architecture direction for complex, high-performance systems.

Deep understanding of system performance and scaling, including interactions among DRAM behavior, high-bandwidth fabrics such as NVLink, and C2C communication.

Strong application-level intuition, including the ability to connect workload algorithms, parallelism, communication, locality, and data movement to architecture choices and measurable outcomes. We value experience with workload characterization, analytical or simulation-based performance modeling, bottleneck analysis, and architecture trade-off evaluation.

We look for a record of identifying cross-domain opportunities that may not be visible when teams optimize individual components separately. We need demonstrated ability to create and advance a multi-generation technical strategy through influence across silicon, systems, software, and application teams.

We value clear communication and sound judgment in ambiguous technical areas, with the ability to explain complex system trade-offs to specialists and executive leaders. We also look for experience mentoring senior engineers into broader architecture leadership roles and building strong technical communities.

Ways To Stand Out from the crowd:

If you have shaped product or technology roadmaps around application-level scaling needs, helped architecture teams build a quantitative understanding of bottlenecks across memory,…