Principal Signal Power Integrity Engineer, Texas Institute Electronics
Listed on 2026-06-22
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Manufacturing / Production
Systems Engineer, Electronics Engineer, Electrical Engineering
Job Posting
Title:
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Hiring Department:
Operational Services and Strategies----
Position Open To:
All Applicants----
Weekly Scheduled
Hours:
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FLSA Status:
To Be Determined at Offer----
Earliest
Start Date:
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Position Duration:
Expected to Continue----
Location:
AUSTIN, TX----
Job Details:
General NotesAbout TIE
The Texas Institute for Electronics (TIE) is a transformative, well-funded semiconductor foundry venture combining the agility of a startup with the scale of a national initiative.
Our MissionA key part of our mission is to advance the state of the art in 3D heterogeneous integration (3
DHI), chiplet-based architectures, and multi-component microsystems- catalyzing breakthroughs across microelectronics, artificial intelligence, quantum computing, high-performance computing, and next-generation healthcare devices.
Backed by $1.4 billion in combined funding from DARPA, Texas state initiatives, and strategic partners, we are building foundational capabilities in advanced packaging and integrated design infrastructure to restore U.S. leadership in microelectronics manufacturing.
Our TechnologyOur 3
DHI and chiplet integration platforms integrate novel thermal management and advanced interconnect solutions to deliver unprecedented performance and energy efficiency. Operating at the intersection of defense electronics and commercial markets, TIE offers a rare opportunity to reimagine an industry from the ground up and build transformative products with global impact.
UT Austin, recognized by Forbes as one of America's Best Large Employers, provides outstanding employee benefits and total rewards packages that include:
Competitive health benefits (employee premiums covered at 100%, family premiums at 50%)
Voluntary Vision, Dental, Life, and Disability insurance options
Generous paid vacation, sick time, and holidays
Teachers Retirement System of Texas, a defined benefit retirement plan, with employer matching funds
Additional Voluntary Retirement Programs:
Tax Sheltered Annuity 403(b) and a Deferred Compensation program 457(b)Flexible spending account options for medical and childcare expenses
Robust free training access through Linked In Learning plus professional conference opportunities
Tuition assistance
Expansive employee discount program including athletic tickets
Free access to UT Austin's libraries and museums with staff
Free rides on all UT Shuttle and Austin Cap Metro buses with staff
For more details, please see:
Benefits | Human Resources and UT Austin Employee Experience | Human Resources
This role is to lead and execute comprehensive Signal Integrity (SI) and Power Integrity (PI) simulations for advanced 2.5D/3.0D heterogeneous integration and multi-material packages. The position will also collaborate with EDA vendors, OSATs, and foundries, and stay current with next-gen interface standards to guide technical strategy and mentor junior engineers.
Responsibilities- Own and drive signal integrity and power integrity (SI/PI) analysis end-to-end for advanced 2.5D/3.0D heterogeneous integration packages-from initial interconnect architecture through silicon-package co-design to final signoff.
- Perform high-speed interconnect modeling and extraction (S-parameters, RLCK, transmission-line models) across TSVs, micro-bumps, hybrid bonds, RDL, and advanced substrates (silicon, glass, organic).
- Architect and optimize power delivery networks (PDN) for multi-chiplet 3D stacks-including target impedance analysis, decoupling strategy, IR-drop simulation, and PDN resonance identification from die through package to board.
- Execute full SI simulation workflows: EM extraction, crosstalk analysis, eye diagram/BER prediction, channel compliance simulation, and jitter budgeting for high-speed interfaces (PCIe Gen6/7, CXL, UCIe, Ser Des, HBM).
- Build and validate SI/PI models for the 3D Assembly Design Kit (ADK)-creating accurate, reusable electrical models that enable chiplet designers to perform system-level co-design against TIE's integration platform.
- Develop reference flows, scripts, and automation that make SI/PI enablement…
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