Senior SoC Chiplet Architect

About the Role

The CEG NAG (Networking Architecture Group) at Intel is an architecture team that defines the future of high‑performance networking silicon. The Senior SoC Chiplet Architect leads architecture strategy for multi‑generation, chiplet‑based SoC platforms targeting next‑generation data‑center workloads.

• Chiplet Architecture Strategy and Roadmap
  • Define monolithic vs. chiplet decision framework and multi‑generation roadmap covering reticle scaling limits, yield economics, modularity and portfolio reuse.
  • Lead architecture studies for 2‑die/3‑die/multi‑chiplet scaling and produce executive‑ready options.
• Chiplet Partition, Resource Scaling, and System Topology
  • Drive functional partitioning across compute, networking/I/O, accelerators, memory and security/management, balancing PPA, D2D bandwidth/latency, validation complexity.
  • Define scalable system resource models (e.g., memory channels, PCIe lanes, pipeline scaling) with respect to chiplet count and topology.
  • Specify logic/gasket and integration constraints for modular assembly and software‑visible behavior.
• Die‑to‑Die (D2D) Interconnect Architecture and QoS
  • Architect high‑bandwidth, low‑latency, reliable D2D communication and define link budgets and QoS mechanisms.
  • Ensure alignment with industry standardization and project‑specific encapsulation.
• Chiplet System Infrastructure:
  Power, Clock/Reset, Boot, Telemetry
  • Define coordinated power delivery, power management flows and clocking/reset distribution across chiplets.
  • Drive chiplet‑aware boot and early firmware architecture with coordinated reset control.
• RAS, Debug, and Observability Across Chiplets
  • Define cross‑chiplet error reporting, containment and recovery policies, and observable diagnostics.
  • Specify debug/trace infrastructure to preserve lab and field diagnosability.
• Quantitative Trade‑Off Studies
  • Lead studies across performance, power, area, cost/yield, and schedule, identifying bottlenecks.
  • Partner with packaging and manufacturing stakeholders for packaging‑overhead trade‑offs.
• Cross‑Functional Technical Leadership
  • Align across architecture, RTL, DV, FW/SW, packaging, and platform teams, leading reviews and converging architectural decisions.
  • Contribute reusable patterns and checklists for chiplet‑based SoC infrastructure.

• Minimum Qualifications
  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or related STEM field.
  • 7+ years of SoC/system architecture experience, including end‑to‑end silicon execution.
  • Experience with multi‑die/chiplet partitioning and related system implications (D2D, boot/reset, cross‑domain QoS, debug).
  • Run architecture trade‑off studies and communicate decisions to senior stakeholders.
• Preferred Qualifications
  • Familiarity with industry chiplet interoperability standards or ecosystem participation.
  • Hands‑on experience in system bring‑up flows and architecture‑driven debug/telemetry planning.
  • Strong fundamentals in interconnects/fabrics, memory subsystem behavior, performance modeling, and PPA trade‑offs.
  • Experience building or consuming cost/yield models for architectural decisions.

Annual salary range: $ – $ USD (based on location and experience). The role offers competitive pay, stock bonuses, and comprehensive benefits covering health, retirement, and vacation. Employees also have a hybrid work model that blends on‑site and remote work per Intel policies.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sexual orientation, or any other protected characteristic. This position does not require or offer sponsorship for immigration assistance beyond what Intel’s policy dictates. Intel does not charge any fees for recruitment or hire, and candidates should report any such request immediately to the recruiter.