Principal Model Researcher

What You'll Be Doing

As Principal AI Model Architect, you will bridge the gap between cutting‑edge AI research and silicon design. Your primary responsibilities include:

• Translating bleeding‑edge transformer, RAN, and attention‑based algorithms into detailed ASIC specifications and SDK lowering requirements, ensuring alignment between research prototypes and production hardware.
• Designing model‑partitioning and tiling strategies to map large, multi‑hundred‑million‑parameter models across heterogeneous compute fabrics, including tensor parallelism, pipeline stages, and memory hierarchies between HBM and on‑chip SRAM.
• Maintaining canonical reference implementations in JAX and PyTorch that serve as the single source of truth for the entire program; validating that the compiled output on silicon matches the research intent bit‑for‑bit.
• Projecting cycle‑accurate performance using simulators, SystemC models, and expert intuition to inform tape‑out decisions and cost‑effective silicon engineering.

You will also collaborate closely with the ASIC and SDK teams to safeguard mathematical correctness and guard against performance regressions.

• Model Architecture Mastery

  You possess deep, battle‑tested knowledge of transformer architectures, including attention head count, KV‑cache sizing, embedding strategies, and trade‑offs between GQA and MQA, and understand how each design decision impacts a hardware execution profile.

• Hardware‑Aware ML

  Experience in a “hardware‑in‑the‑loop” environment, evaluating cache line behavior, memory bottlenecks between HBM and SRAM, and the effects of SIMD and VLIW units on model shapes.

• Framework Depth

  Advanced proficiency in JAX (preferred), PyTorch, or Tensor Flow at the export and compilation layer, comfortable with graph capture, XLA compilation, and StableHLO representations.

• Performance Modeling

  Hands‑on experience with SystemC, transaction‑level modeling, or custom cycle‑accurate simulators to validate architectural choices before silicon commitment.

• Preferred Expertise
  • Telecommunications DNA

    Applied AI to real RAN workloads such as channel estimation, beamforming, and interference management; understand why 5G inference presents unique challenges beyond data‑center workloads.

  • Compiler Curiosity

    Deep understanding of the journey from high‑level compute graphs to hardware‑bound execution sequences and instinctive ability to protect against information loss in that translation.

  • Numeric Sensitivity

    Experience with complex‑valued AI models and the challenges of fixed‑point quantization, dynamic range, and precision‑reduction stability when mapping to DSP and matrix accelerators.

DISCLAIMER:
The above statements are intended to describe the general nature and level of work being performed by employees in this position. They are not an exhaustive list of all responsibilities, duties, and skills required for this position, and you may be required to perform additional job tasks as assigned.

Ericsson is proud to be an Equal Opportunity Employer. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity employer, learn more.