Firmware Engineer II

Job Description

Be part of the Cadence DDR PHY IP Front End Design team responsible for:

• Develop firmware for DDR5 PHY using microcontrollers
• Developing firmware in C typically involving bare‑metal programming and developing low‑level APIs on microcontrollers
• Collaborating with hardware designers and memory subsystem architects to derive training algorithms and implement them
• Collaborating with the verification team to deduce firmware‑hardware co‑verification plans
• Develop and debug firmware in RTL‑based hardware simulations (C + Verilog simulations)
• Develop and debug on silicon bring‑up boards

• Good knowledge of DDR5 JEDEC spec, knowledge of different DIMM configurations and specifications
• Relevant experience in developing bare‑metal firmware for high‑speed Ser Des or memory interface physical layer blocks
• Good knowledge of C programming language for embedded software development and use of relevant IDE
• Comfortable debugging RTL simulations involving firmware and microcontroller subsystem
• Good knowledge of Shell/Perl/Python/TCL scripting
• Good experience on verification EDA tools like simulators and waveform viewers

Cadence is committed to equal employment opportunity throughout all levels of the organization. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.