ASIC Static Timing and Synthesis Engineers

ASIC Static Timing and Synthesis Engineers (00005)

Client:
Northrop Grumman

Position: ASIC Static Timing and Synthesis Engineers (00005)

Duration:
Long term contract (a year+) or CTH (NG will offer FT opportunity after a year for the right candidate, if candidate is interested)

Clearance:
Active Secret (No interim or inactive)

Job Description:

STA (Static Timing Analysis) Design Engineer - looking for experienced Timing Analysis & Sign-off expert for complex digital design. The engineer will be responsible for owning & working with team on constraint development, timing closure using latest nanometer technologies.

• Work with systems architect/IP experts to develop level timing constraints
• Work with physical design team on design constraint and timing closure
• Be hands‑on technical individual contributor

• Secret government clearance within last 5 years
• Good knowledge of EDA tools and scripting
• BSEE with 8 years of experience or MSEE with 5 years’ experience in static timing & RTL Design
• Must be a very good team player with a very good oral, written and interpersonal communication skills

• Synopsys Primetime‑SI, Synopsys Design Compiler, Cadence Encounter Timing system
• Scripting languages – tcl, csh, perl, Makefile
• Operating systems: linux, windows
• Revision control: SVN, git
• Experience with RTL synthesis
• Experience with ARM CPUs, peripherals such as I2C, SPI, UART, Asynchronous interface designs, peripherals and interconnect protocols such as AHB, AXI, PCIE etc

All your information will be kept confidential according to EEO guidelines.