Assistant Research Scientist; PREP

PREP Research Associate

This position is part of the National Institute of Standards (NIST) Professional Research Experience (PREP) program. NIST recognizes that its research staff may wish to collaborate with researchers at academic institutions on specific projects of mutual interest, thus requires that such institutions must be the recipient of a PREP award. The PREP program requires staff from a wide range of backgrounds to work on scientific research in many areas.

Employees in this position will perform technical work that underpins the scientific research of the collaboration.

Security Evaluation and Mitigation of Cross-Chiplet Vulnerabilities in Heterogeneous Integration.

This project directly addresses the semiconductor industry's need for secure and trustworthy heterogeneous integration, aligning with national security priorities and trusted microelectronics goals.

• Research on threats to security of heterogeneous integration, including formal threat modeling, metrics for evaluating security leakage and mitigation effectiveness, and attack simulations.
• Research and develop a security evaluation framework for identifying and characterizing vulnerabilities across chiplets, inter-chiplet interfaces, shared interconnects, memory controllers, and other system-level resources.
• Engage stakeholders across industry, academia, and government to align security requirements, research priorities, evaluation methods, and adoption pathways, incorporating insights from workshops and ongoing collaborations.
• Focus on emerging areas such as advanced packaging and chiplet-based systems, developing actionable countermeasures and publishing findings for industry use.
• Identify, research, and document methods to support secure and interoperable security assessment across heterogeneous integrated systems, including benchmarks, test methodologies, metrics, and machine-readable reporting formats suitable for large-scale deployment.

• § Developing a security evaluation and mitigation framework for heterogeneous integration, with an initial focus on multi-tenant computing platforms.
• § Addressing emerging vulnerabilities across chiplets, interposers, interfaces, and integrated components, while enabling trusted, scalable, and privacy-preserving communication within heterogeneous systems.
• § Developing and evaluating practical mitigation techniques that reduce security leakage while preserving system performance, scalability, and design flexibility across different chiplet architectures, interconnect topologies, and integration configurations.
• § Documenting results and developing publishable material for consumption by semiconductor engineers.
• § Presenting results at internal meetings, and occasional meetings with external stakeholders.

• § Enrolled in a PhD program in Computer Engineering, Computer Science, Electrical Engineering, or a related field.
• § Familiarity with integrated circuit design and threat analysis methodologies.
• § Strong technical expertise in general-purpose programming languages, including C/C++, Python, and MATLAB, as well as hardware description languages widely used in the semiconductor industry, such as Verilog HDL.
• § Expertise in open-source computer architecture and interconnect simulation tools, including gem5, Noxim, Sniper, and Lego Sim, as well as leading commercial design and verification tools from Cadence and Synopsys, such as Cadence Innovus and Synopsys Design Compiler.
• § Knowledgeable in Cybersecurity tenets.
• § Ability to integrate information from diverse sources effectively and efficiently.
• § Strong oral and written communication skills.
• § US citizenship is preferred

The referenced salary range represents the minimum and maximum salaries for this position and is based on Johns Hopkins University's good faith belief at the time of posting. Not all candidates will be eligible for the upper end of the salary range. The actual compensation offered to the selected candidate may vary and will ultimately depend on multiple factors, which may include the successful candidate's geographic location, skills, work experience, internal equity, market conditions, education/training and other factors, as reasonably determined by the University.

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