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Sr. FPGA Developer; Hybrid- Aberdeen Proving Ground, Maryland

Job in Bear, New Castle County, Delaware, 19701, USA
Listing for: Fairwinds Technologies, L
Full Time position
Listed on 2026-07-08
Job specializations:
  • Engineering
    Electronics Engineer, Systems Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 150000 - 175000 USD Yearly USD 150000.00 175000.00 YEAR
Job Description & How to Apply Below
Position: Sr. FPGA Developer (Hybrid- Aberdeen Proving Ground, Maryland)

If you are unable to complete this application due to a disability, contact this employer to ask for an accommodation or an alternative application process.

5 days ago Requisition

Salary Range: $ To $ Annually

Location: Aberdeen Proving Ground (APG), MD Type:
Hybrid (Up to 40 hours/week in-office as needed)

About Fairwinds Technologies

Fairwinds Technologies is a U.S.

-based engineering firm specializing in Satellite Communications (SATCOM), RF Transmission Systems, Network Design, Systems Integration, and Digital Signal Processing (DSP). We support Command, Control, Communications, and Computer (C4) systems in austere military environments, delivering advanced communications, networking, and IT solutions to defense and civilian agencies worldwide.

Position Overview

We are seeking an FPGA Design Engineer with strong experience developing programmable logic solutions using Xilinx Vivado, Verilog, and VHDL, targeting Xilinx Zynq Ultra Scale+ RFSoC, MPSoC, and Versal platforms. The ideal candidate has hands‑on experience designing, implementing, and validating FPGA‑based signal processing, RF data path, and high‑speed data movement architectures. This includes implementing complex DSP algorithms provided by DSP engineers, integrating with high‑speed data converters (e.g., Analog Devices ADRV series, Texas Instruments AFE/ADC), and designing multi‑sample per clock architectures for wideband RF applications.

The candidate should have worked closely with DSP and embedded software engineers to deliver complete system solutions.

This role focuses on programmable logic (PL) development, including RTL design, simulation, synthesis, timing closure, and hardware validation on PCB‑based platforms. The engineer will collaborate across hardware, DSP, RF, and embedded Linux/software domains to support mission‑critical communications and signal processing systems.

This position reports to the Chief Technology & Strategy Office and involves close collaboration with customers and engineering teams to deliver innovative solutions for RF Tactical & Naval Military Solutions, as well as strategic border protection applications.

Key Responsibilities
  • Design, implement, and verify FPGA logic using Verilog and VHDL within the Xilinx Vivado toolchain for Zynq Ultra Scale+ RFSoC, MPSoC and Versal devices.
  • Develop programmable logic architectures for signal processing, control, and high‑speed data movement applications.
  • Implement complex DSP algorithms provided by DSP engineers into efficient FPGA fabric designs (filters, FFTs, channelize rs, modulators, demodulators, decimation/interpolation, fixed‑point optimization).
  • Work with embedded software engineers to define and implement PL–PS interfaces, including AXI-Lite, AXI-Stream, DMA, interrupts, and register maps.
  • Integrate FPGA designs with embedded processors and heterogeneous compute architectures (e.g., Zynq Ultra Scale+ MPSoC, RFSoC, Versal ACAP).
  • Perform functional simulation, static timing analysis, and resource optimization to meet performance, latency, and power constraints.
  • Support FPGA bring‑up and debugging on custom PCB hardware using lab tools such as JTAG, Integrated Logic Analyzer (ILA), logic analyzers, and oscilloscopes.
  • Participate in system integration and debug efforts spanning FPGA logic, embedded software, DSP algorithms, and hardware.
  • Develop test benches, validation strategies, and design documentation, including FPGA design descriptions, interface control documents (ICDs), and SBIR deliverables as required.
  • Support prototype‑to‑production transitions, including ECOs, version control, and configuration management.
  • Design and integrate interfaces with high‑speed data converters from Analog Devices (e.g., ADRV
    9009, AD9081) and Texas Instruments, including JESD
    204B/C and LVDS interfaces.
  • Develop multi‑sample per clock (parallel sample) architectures to meet throughput requirements for wideband RF signal processing applications.
  • Apply fundamental RF signal processing knowledge to support digital front‑end design including NCOs, mixers, digital up/down conversion, and gain control.
Required Qualifications
  • Bachelor’s degree in Electrical Engineering, Computer…
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