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Timing Design Engineer – ASIC Sign-off & Constraints

Job in Beaverton, Washington County, Oregon, 97078, USA
Listing for: Apple
Full Time position
Listed on 2026-01-25
Job specializations:
  • Engineering
    Engineering Design & Technologists, Manufacturing Engineer, Hardware Engineer, Electronics Engineer
Job Description & How to Apply Below
A leading tech company in Beaverton is looking for an ASIC STA Engineer responsible for timing sign-off and flow development. The ideal candidate will possess over 2 years of experience in ASIC timing constraints, proficiency in STA tools like Primetime, and strong communication skills. You will collaborate with RTL designers and the Physical Design team to innovate timing constraints and ensure timing closure.

Join us to make a difference and contribute to cutting-edge technology.
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