Senior ASIC Design Engineer – RTL & SoC Integration

A technology leader is seeking an experienced ASIC Design Engineer to join their innovative team in Beaverton, Oregon. In this role, you will be responsible for SOC design, collaborating with various specialists, and writing specifications for complex logic designs. The ideal candidate has a Bachelor’s degree and a minimum of 10 years of relevant industry experience, particularly in Verilog RTL Logic Design.

This position offers the chance to engage in cutting-edge design processes, contributing to transformative hardware technologies.
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