Analog Layout Engineer

Description

Analog Layout engineers are pivotal in delivering Analog Mixed‑Signal IP in a SOC flow. You will collaborate with teams of highly skilled individuals to develop the next generation of world‑leading SOCs. Your responsibilities include crafting sophisticated layouts for mixed‑signal and analog circuits, reviewing floor plans, and analyzing intricate circuits with circuit designers. You'll run complete sets of design verification tools, plan/schedule work, and coordinate vital layout tradeoffs.

Interpretation of LVS, DRC, and ERC reports is key to finding the fastest way to complete the layout, exceeding engineering specifications and expectations.

• BS and a minimum of 10 years relevant industry experience.

• 10+ years of experience in analog/mixed‑signal layout design, with a focus on deep submicron CMOS circuits and at least 3+ years in FinFET technologies.
• Programming/scripting knowledge in SKILL, Perl, TCL, Shell, and/or Python.
• Familiar with Machine Learning and AI concepts.
• Experience with ultra‑high speed ADC/DAC.
• Proven Expertise in implementing analog layout designs, achieving tight matching, low noise, and low power consumption.
• Must recognize failure‑prone circuit and layout structures, have experience with analog and DFM standards, and be able to identify the best approach to solving problems.
• High Proficiency in custom and standard cell‑based floor‑planning and hierarchical layout assembly.
• Technical understanding of IR drop, RC delay, electromigration, self‑heating, and coupling capacitance.
• High Proficiency in interpreting physical verification reports (DRC, ERC, LVS, etc.).
• Experience using Cadence Virtuoso's advanced features (XL, EAD, APR, and Constraint Manager).
• Excellent communication skills and ability to work with cross‑functional teams.
• Cadence Innovus.
• PCell creation experience.
• MSEE or Ph.D. in Electrical and Computer Engineering.

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