SoC Physical Design Methodology Engineer

SoC Physical Design Methodology Engineer

As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions.

• Perform various types of physical verification checks such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography at the chip and block level.
• Collaborate with the CAD/Technology teams for flow bring up and validation, work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout.
• Lead schedules and support cross‑functional engineering efforts.
• Work on padring, bump, RDL design, and work with the package and floorplan teams.

• BS and 10+ years of relevant industry experience.

• Experienced with physical verification flows such as DRC/LVS/ANT/HVDRC signoff flows and full‑chip integration methodology.
• Experience with ESD and macro placement design guidelines, digital and analog mixed‑signal back‑end verification checks and methodology.
• Knowledge of all aspects of ASIC physical design and physical verification checks for hierarchical designs including full‑chip flows.
• Scripting skills perl/python/tcl to debug flow related issues and automate checks.
• Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc.
• Tapeout experience with a track record of successful signoffs.
• Layout design experience is a plus.

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