SoC Physical Design Engineer, STA​/Timing

SoC Physical Design Engineer, STA/Timing Description

• Work with design teams to understand and debug constraints and facilitate logic changes to improve timing.
• Work with the Physical Design team, highlighting issues and best practices.
• Help create timing ECO’s for project tapeout.
• Create and maintain scripts and methodologies for analysis and runs.
• Create documentation and help with guidelines/specs.
• Deep analysis of timing paths to identify key issues.
• Implement timing infrastructure.

• Minimum Bachelor's degree with 0+ years of experience
• Experience with STA.
• Experience with noise, crosstalk, and/or OCV effects.

• Familiar with important aspects of timing of large high-performance SoC designs in sub-micron technologies.
• Experience with STA and methodologies for timing closure.
• Familiar with circuit modeling, including SPICE models, and/pr worst-case corner selection.
• Good programming skills with Perl and TCL.
• Experience with large design STA and Timing Closure.
• Familiar with ECO techniques and implementation.
• Good communicator who can accurately describe issues and follow them through to completion.

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