Emulation Verification Engineer

Description

As a member of the Emulation verification team, we play a key role in using Emulation for verification of large SoCs. The overall work will involve porting the design onto the Palladium platform, followed by completing the detailed Emulation testplans.

• Collaborate closely with Architecture, Design, DV, Silicon Validation, Power and SW teams to bring up large SoCs on emulation platform
• Develop/apply synthesizable monitors/checkers, stimulus on emulation platform
• Prepare and complete the test plan and perform reviews with the multi-functional teams
• Perform low power testing on emulation platform
• Develop code for Design and verification that aids with emulation activities, using Verilog/System Verilog/UVM
• Develop random stimulus infrastructure by reusing existing UVM simulation constraints

• Minimum of BS + 3 years relevant industry experience.

• Understanding of the tool flow from RTL to Emulation is a huge plus
• Good understanding of any Standard Emulator (Palladium, Veloce, Zebu) OR FPGA (Xilinx, Altera) flow
• Experience in writing Synthesize-able System Verilog/Verilog code and System Verilog assertions
• Experience with System Verilog verification environments including C/C++ DPI, UVM
• Experience with writing and debugging test FW
• Experience on any Scripting (Perl/Python/TCL)
• Excellent analytical and debug skills
• Experience in UVM Acceleration is plus.

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