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SystemC​/TLM-Modeling Engineer — CPU Subsystem; Temporary

Job in Town of Belgium, Belgium, Ozaukee County, Wisconsin, 53004, USA
Listing for: Euraxess
Full Time, Seasonal/Temporary, Contract position
Listed on 2026-06-06
Job specializations:
  • Engineering
    Systems Engineer
Salary/Wage Range or Industry Benchmark: 80000 - 100000 USD Yearly USD 80000.00 100000.00 YEAR
Job Description & How to Apply Below
Position: SystemC/TLM-2.0 Modeling Engineer — CPU Subsystem (Temporary Assignment)
Location: Town of Belgium

Organisation/Company IMEC Research Field Engineering Researcher Profile Recognised Researcher (R2) Positions Other Positions Final date to receive applications 31 Jul 2026 - 12:00 (Europe/Brussels) Country Qatar Type of Contract Temporary Job Status Full-time Hours Per Week 40 Offer Starting Date 1 Aug 2026 Is the job funded through the EU Research Framework Programme? Not funded by a EU programme Is the Job related to staff position within a Research Infrastructure?

No

Offer Description

Build the virtual platforms that turn imec's CPU architectures into runnable systems — before silicon.

Compute System Architecture (CSA) is imec's center of excellence for hardware-software-technology co-design of future compute systems. We work in close collaboration with imec's expertise centers in applications, technology, circuits, and design to innovate and pathfind next-generation compute architectures across AI, HPC, automotive, space, and other domains. CSA operates across six imec centers — Belgium, the Netherlands, Germany, the UK, the USA, and Qatar.

This position is based primarily in Leuven, Belgium.

We are looking for a System

C / TLM-2.0 Modeling Engineer to join the Platform, Prototypes and Physical-Aware Design (P3D) group, focusing on the CPU subsystem of imec's RISC-V-based compute platforms. You will develop System

C TLM-2.0 models of CPU cores, caches, memory hierarchy, and the surrounding interconnect — enabling architectural exploration, early software enablement, and pre-silicon performance analysis.

Your models are the bridge between architecture and implementation: they let our architects evaluate design choices before committing to RTL, they let software teams start porting and tuning long before silicon is back, and they feed directly into the validation infrastructure that surrounds imec's prototype demonstrators — the silicon vehicles for imec's CMOS 2.0 vision of functionally partitioned, 3D-integrated compute systems beyond what monolithic SoCs can deliver.

What you will do

  • Develop System

    C TLM-2.0 models of the CPU subsystem — cores, caches, memory controllers, on-chip interconnect — at both loosely-timed (LT) and (Use the "Apply for this Job" box below). levels.
  • Assemble and maintain virtual platforms that integrate these models with peripheral and system IP, enabling full-system simulation and early software bring-up.
  • Drive architectural exploration studies in close collaboration with SoC and chiplet architects: micro-architectural what-ifs, partitioning trade-offs, memory hierarchy sweeps, and chiplet interconnect dimensioning for CMOS 2.0 systems.
  • Define and run pre-silicon performance analysis flows — workload characterization, bottleneck identification, and PPA-relevant trade-off studies.
  • Support hybrid RTL/TLM co-simulation environments to validate model fidelity against RTL implementations and to accelerate RTL verification with TLM-driven stimulus.
  • Collaborate with the RTL design and verification teams to align model behaviour with implementation and to feed insights back into the architecture loop.
  • Document model intent, assumptions, and known limitations clearly enough that architects, designers, and software engineers can rely on the model with confidence.
  • This is a temporary contract of two years, with the possibility to extend the contract.
  • At least 5 years of hands-on experience developing System

    C models with TLM-2.0 for CPU, SoC, or memory subsystems.
  • Strong modern C++ (C++11 and beyond), with the discipline to write models that are fast, maintainable, and trustworthy.
  • Solid understanding of CPU and SoC architecture — pipelines, caches, coherency, memory ordering, interconnect protocols — at a level that lets you turn an architectural spec into a faithful executable model.
  • Practical familiarity with both LT and AT modeling styles and the trade-offs between simulation speed and timing fidelity.
  • Experience building or extending virtual platforms (e.g. Synopsys Virtualizer, Arm Fast Models, Imperas, gem5, QEMU, or in-house frameworks).
  • Comfort with scripting (Python, Tcl) for model build flows, regressions, and analysis automation.
  • Excellent written and spoken English, with the…
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