Digital Designer — CPU Subsystem; RTL & Verification; Temporary

Organisation/Company IMEC Research Field Engineering Researcher Profile Recognised Researcher (R2) Positions Other Positions Final date to receive applications 31 Jul 2026 - 12:00 (Europe/Brussels) Country Qatar Type of Contract Temporary Job Status Full-time Hours Per Week 40 Offer Starting Date 1 Aug 2026 Is the job funded through the EU Research Framework Programme? Not funded by a EU programme Is the Job related to staff position within a Research Infrastructure?

No

Design and verify the CPU subsystem at the heart of imec's RISC-V compute prototypes.

Compute System Architecture (CSA) is imec's center of excellence for hardware-software-technology co-design of future compute systems. We work in close collaboration with imec's expertise centers in applications, technology, circuits, and design to innovate and pathfind next-generation compute architectures across AI, HPC, automotive, space, and other domains. CSA operates across six imec centers — Belgium, the Netherlands, Germany, the UK, the USA, and Qatar.

This position is based primarily in Leuven, Belgium.

We are looking for a Digital Designer to join the Platform, Prototypes and Physical-Aware Design (P3D) group, with a focus on the CPU subsystem of imec's RISC-V-based compute platforms. You will own RTL design of CPU-side blocks — pipelines, caches, memory hierarchy, and the surrounding interconnect logic — and drive their verification from unit-level testing through subsystem-level integration.

Your work directly feeds imec's prototype demonstrators, the silicon vehicles for imec's CMOS 2.0 vision: functionally partitioned, 3D-integrated compute systems that push well beyond what monolithic SoCs can deliver. You will work on technology beyond 2nm, alongside principal SoC and chiplet architects, in a fast-moving research environment with high industrial visibility.

• Translate microarchitectural specifications into clean, synthesizable RTL (System Verilog) for CPU subsystem blocks — front-end, execution pipeline, load/store unit, caches, and on-chip memory interfaces.
• Integrate RISC-V cores with surrounding subsystem components: cache hierarchies, coherency logic, AXI/CHI interconnects, and debug/trace infrastructure.
• Develop and execute functional verification environments for the modules you design — test benches, UVM agents, System Verilog assertions, coverage models — and drive coverage closure to tape-out quality.
• Collaborate closely with SoC and chiplet architects to refine specifications, resolve ambiguities, and feed implementation insights back into the architecture loop.
• Anticipate PPA, timing, and floorplan implications in your RTL, supporting physical-aware design iterations through to prototype tape-out.
• Contribute to verification IP, regression infrastructure, and design/verification flow improvements used across the group.
• Document design and verification intent clearly enough that the next engineer — or the next prototype — can build on it.
• This is a temporary contract of two years, with the possibility to extend the contract.
• At least 5 years of hands-on RTL design experience in System Verilog/Verilog for CPU, GPU, or similarly complex digital subsystems.
• Solid grasp of CPU microarchitecture — pipelines, hazards, branch prediction, caches, memory ordering — at a level that lets you read an architectural spec and turn it into RTL with sound design choices.
• Strong functional verification capability: UVM, System Verilog assertions (SVA), coverage-driven verification, constrained-random stimulus, and debug discipline.
• Familiarity with one or more standard interconnect protocols (AXI, ACE, CHI, Tile Link) at both RTL and verification level.
• Hands-on experience with industry EDA flows (Synopsys, Cadence, Siemens) for simulation, lint, CDC, and synthesis.
• Comfort with scripting (Python, Tcl, Make) for verification automation, regressions, and design integration.
• Excellent written and spoken English, with the documentation habits to match.
• A structured, transparent way of working and a collaborative attitude in a multidisciplinary, multicultural team.

Considered an asset:

• Experience with RISC-V cores (in-order or…