I​/O Cells ESD Design and IBIS Modeling

Overview

Master internship – Leuven.
Type of internship: Master internship.
Duration: 6 months.
Required educational background: Electrotechnics/Electrical Engineering.
Reference code: 2026-INT-180.
Allowance: Imec allowance will be provided.

The internship project addresses two practical challenges in I/O circuit design and reliability at advanced CMOS technology nodes. First, establish a validated IBIS modeling flow for high-speed I/O standards, starting with LVDS. This involves running SPICE-level simulations of transmitter and receiver behavior, generating IBIS models through existing toolflows, and verifying their accuracy by correlating SPICE and IBIS simulation results. A reusable testbench and clear documentation will be produced so that the flow can be applied to future I/O standards with minimal rework.

Second, target ESD robustness of a bidirectional I/O cell in GF 22 nm technology, where a known ESD failure has been identified. The intern will reproduce the failure in simulation, identify the root cause in terms of device stress and ESD requirements, and propose and verify circuit-level solutions that reduce voltage overstress on 1.8 V devices during ESD events. Both tasks are expected to produce working simulation flows, verified results, and reusable documentation that can support ongoing and future I/O design and reliability work within the team.

Currently enrolled in a Master’s program in Electrotechnics or Electrical Engineering with experience in high-speed I/O design and simulation tools. Familiarity with SPICE, IBIS, CMOS technology, and ESD concepts is desirable.