Senior DTCO DRAM Periphery Circuit Designer/Architect
Listed on 2026-07-18
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Engineering
Electronics Engineer, Hardware Engineer, Systems Engineer
Location: Town of Belgium
Senior DTCO DRAM Periphery Circuit Designer / Architect What you will do
In this position, you will join imec’s memory design and pathfinding activities and take a leading role in the design and exploration of advanced DRAM periphery circuits. You will work on the circuits that enable full DRAM operation, with a strong understanding of how they interact with the memory array, the array hierarchy, and the external DRAM protocol.
You will work on bringing silicon proof-of-concepts to tapeout, bridging transistor-level circuit design, array organization, and macro-level architecture, with the objective of enabling robust, high-performance, and energy-efficient DRAM solutions.
You will design, analyze, and optimize key DRAM peripheral building blocks such as row and column path circuitry, wordline-related drivers, sense-amplifier-related functions, write-path circuits, precharge and equalization functions, control and timing logic, data-path and address-path circuitry, and voltage-generation or regulation blocks where relevant.
You will be expected to understand the complete DRAM access flow, including array activation, read, write, precharge, refresh-related behavior, and the protocol timing implications of these operations. You will work in a layout-aware manner, taking ownership from specification through circuit design, simulation, verification, and implementation readiness.
You will also contribute to architectural decisions at subarray, bank, and macro level by understanding the trade-offs between performance, power, area, robustness, and technology assumptions, for emerging technologies. The role therefore requires not only strong block-level design capability, but also the ability to reason across array organization and protocol-level operation.
What we do for youWe offer a full-time position in a highly innovative and multidisciplinary environment, with the opportunity to work on advanced memory technologies and future-oriented DRAM solutions. This is a chance to work in a rapidly growing, multi-disciplinary team with strong interaction across circuit design, devices, process integration, and system-facing research.
This is an exciting role with significant technical ownership and visibility, where your work will directly contribute to memory roadmap definition, circuit innovation, and demonstrator or test-chip activities. Internal imec job-description material explicitly frames these roles around enabling future semiconductor memory technologies and interacting with major foundry, fabless, and EDA partners in imec’s ecosystem. You will have the opportunity to collaborate closely with circuit designers, device experts, process integration engineers, architects, and DTCO/STCO teams, while influencing how advanced memory concepts are translated into practical circuit and macro implementations.
We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, "our corporate university", we actively invest in your development to further your technical and personal growth.
We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits.
Who you are- You have a Master’s degree or PhD in Electrical Engineering, Electronics, or a related field.
- You bring strong industrial experience in DRAM design, with at least 6 years in the DRAM industry focused on periphery circuit design.
- You have deep understanding of DRAM array organization and the interaction between array, periphery, and protocol. This includes familiarity with array hierarchy, subarrays, banks, rows, columns, row-buffer behavior, and the main operational sequences associated with DRAM access.
- You have hands‑on experience designing and analyzing DRAM peripheral circuits and understand the role of the main DRAM submodules, including row and column path circuitry,…
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