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Low-power and Secure Cryptographic Circuits for Flexible Healthcare Patches

Job in Town of Belgium, Belgium, Ozaukee County, Wisconsin, 53004, USA
Listing for: KU LEUVEN
Full Time, Part Time position
Listed on 2026-08-02
Job specializations:
  • Engineering
    Research Scientist, Electrical Engineering, Electronics Engineer
  • Research/Development
    Research Scientist, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 36836 - 47197 USD Yearly USD 36836.00 47197.00 YEAR
Job Description & How to Apply Below
Location: Town of Belgium

Organisation/Company KU LEUVEN Research Field Engineering » Electronic engineering Computer science » Digital systems Researcher Profile First Stage Researcher (R1) Final date to receive applications 5 Aug 2026 - 23:59 (UTC) Country Belgium Type of Contract To be defined Job Status Full-time Offer Starting Date 1 Oct 2026 Is the job funded through the EU Research Framework Programme? Not funded by a EU programme Reference Number BAP
- Is the Job related to staff position within a Research Infrastructure? No

Offer Description

Integrated circuits based on flexible thin-film transistors have received lots of attention due to recent progress in literature and the pioneering aspect of multi-project wafers with thin-film transistor foundries. The targeted semiconductor is Indium-Gallium-Zinc-Oxide (IGZO) from the UK-based foundry Pragmatic. IGZO is attractive due to a simple process flow and potential small channel lengths on flexible substrates.
This PhD topic is part of the LOGICARE project that concentrates on low-power and secure flexible healthcare patches. The project starts from the observation that established assumptions for side-channel leakage and countermeasures in conventional CMOS technology cannot be directly transferred and must be re-evaluated in the context of flexible electronics.
The key application is to design flexible chips for low-power and side-channel protected authenticated encryption in next-generation wearable healthcare applications. It will be your task to perform a detailed system level study, to design the targeted circuits for tape out and to characterize the manufactured circuits. The characterization can occur at our ES&S lab at Campus Diepenbeek. It will be important to understand the opportunities of the specific technologies, and to overcome the challenges related to the flexible technology.

  • You have a master's degree in electrical engineering or engineering technology.
  • You have good basic knowledge and hands-on experience in digital electronics and have a keen interest in technology-aware design activities.
  • You have a good knowledge of VLSI IC design, and Cadence has no secrets to you.
  • You master the tape out flow for chips.
  • You can work independently and pro-actively, you are well-organized, accurate and stress resistant.
  • You are analytical, flexible, result-oriented, customer and market oriented.
  • You are an enthusiastic and enterprising team player with innovative ideas that searches for improvements, experiments with new concepts and solves problems in a creative and clear manner.
  • You want to dedicate yourself to spreading the mission and values of the faculty: you are open to other cultures and world views and you are motivated to work internationally.

The successful candidate will be offered a PhD fellowship to become part of our team to work towards a PhD under the supervision of Prof. Nele Mentens and Prof. Kris Myny. This full-time mandate, for which funding is secured for the full duration of the PhD, is initially limited to a 1-year contract with a possible extension depending on the performance of the candidate.

The final goal will be obtaining a PhD after 4 years.

The successful candidate will be offered a PhD fellowship to become part of our team to work towards a PhD under the supervision of Prof. Nele Mentens and Prof. Kris Myny. This full-time mandate, for which funding is secured for the full duration of the PhD, is initially limited to a 1-year contract with a possible extension depending on the performance of the candidate.

The final goal will be obtaining a PhD after 4 years.

Eligibility criteria

  • You have a master's degree in electrical engineering or engineering technology.
  • You have good basic knowledge and hands-on experience in digital electronics and have a keen interest in technology-aware design activities.
  • You have a good knowledge of VLSI IC design, and Cadence has no secrets to you.
  • You master the tape out flow for chips.
  • You can work independently and pro-actively, you are well-organized, accurate and stress resistant.
  • You are analytical, flexible, result-oriented, customer and market oriented.
  • You are an enthusiastic and enterprising team player with innovative ideas that searches for improvements, experiments with new concepts and solves problems in a creative and clear manner.
  • You want to dedicate yourself to spreading the mission and values of the faculty: you are open to other cultures and world views and you are motivated to work internationally.
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