Sr UCIe Phy Expert, Annapurna Labs

Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.

• As a senior member of the platform development team, participate in the definition, design and validation of AWS next generation ML chips, cards and server integration, with a focus on HBM, DDRx, memories and Serdes topics.
• Independently work with vendors, understand settings, write/modify tests, debug and collect data in the fleet.
• Collaborate with architects, design teams and software engineers to deliver the next generation ML chip, including IP integration, 2.5D design, bring up, characterization and validation.
• Contribute to operational excellence, code reviews, design discussions, team planning, and ticket/metric/COE reviews; mentor others and participate in interviews.
• Support the physical design team by reviewing clocking and timing constraints; drive cross-functional triage on complex functional and performance issues; lead post-silicon bring-up for UCIe-Advanced or Standard systems; define boot-up initiation, reset flow, training sequence; perform system-level debug and root-cause analysis through bring-up, characterization, validation and production phases.

Our team is dedicated to supporting new members. We have a broad mix of experience levels and tenures, and we’re building an environment that celebrates knowledge-sharing and mentorship. Our senior members enjoy one-on-one mentoring and thorough, but kind, code reviews. We care about your career growth and strive to assign projects that help our team members develop your engineering expertise so you feel empowered to take on more complex tasks in the future.

• BS or MS in EE, ECE or CS; 7+ years of experience in Silicon development with 3+ years in SOC/IO/Subsystems; good understanding of UCIe at the PHY and controller level
• Good knowledge of UCIe training, timing parameters and/or controller features
• Drive the IP Integration and design of silicon and 2.5D packaging
• Support the physical design team, review clocking and timing constraints
• Drive cross-functional triage effort on complex functional and performance issues
• Take the leadership role in post-silicon bring-up of UCIe-Advanced or Standard
• Define boot-up initialization, reset flow, training sequence; perform system-level debug and root-cause analysis through bring-up, characterization, validation and production phase
• Experience working with 3rd party IP

• Strong Firmware development skills within embedded environments
• Good leadership skills and ability to multi-task and thrive in a dynamic environment
• Knowledge of UCIe phy and controller related protocols; good communication and interpersonal skills

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The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave.

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USA, TX, AUSTIN -  -  USD annually

USA, TX, Austin -  -  USD annually

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Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.