Design Verification & Validation Engineer

Overview

Location: USA – Texas Austin;
Employment Type: Permanent;
Experience

Required:

5 – 10 Years (Minimum 3 years in Design Verification);
Compensation: USD 160000 – 180000

Position Overview
:
The Verification Engineer will lead RTL design verification for high-speed digital systems. This role focuses on building verification environments, executing test strategies, and ensuring full functional coverage while collaborating with design and architecture teams.

• Develop and execute verification plans based on design specs
• Build and maintain SV/UVM environments
• Define and close functional and code coverage
• Debug RTL and support regression testing
• Participate in reviews, test planning, and sign-off
• Document results and collaborate cross-functionally

• 5 years in digital/RTL engineering
• 3 years in design verification
• Strong knowledge of VLSI verification flows
• Hands-on with System Verilog & UVM (or equivalent)
• Strong debugging and problem-solving skills

• Protocol/datapath verification experience (Ethernet preferred)
• Mixed-signal exposure
• Strong documentation and communication skills