Signal Integrity​/Power Integrity; SI​/PI Lead

Role Summary

Own SI/PI strategy and execution across board and system design to ensure signal integrity, power integrity, and performance scaling for next-generation AI and server platforms. Member of the CTO Architecture team, with ownership of SI/PI architecture and product definition in this domain.

• Define and drive SI/PI methodologies, models, and design rules
• Lead simulation and validation for high-speed interfaces (PCIe, DDR, Ser Des, high-speed fabrics)
• Collaborate with board and platform architects to co-optimize architectures and layouts
• Identify and resolve signal and power issues early in the design cycle
• Lead SI/PI team's methodologies and validation across design, bring-up, and production
• Drive continuous improvement in tools, flows, and best practices
• 10–15+ years in SI/PI for high-performance systems
• Expertise in high-speed signaling, channel modeling, and power delivery networks
• Hands-on experience with SI/PI tools and lab validation
• Strong collaboration across board, package, and system teams
• Experience in server or AI infrastructure strongly preferred

• Work across multiple silicon and technology ecosystems
• Architect systems from concept through global, rack-scale deployment
• Engage directly with hyperscaler and AI-native customers
• Operate at the intersection of platform design, manufacturing, and scaled deployment

Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.