US_East | Electrical​/Electronics & Semiconductors Engineer_L

Position: US_East | Electrical / Electronics & Semiconductors Engineer_L3
Description:

"Possible 3 Month CTH | No Fees | Do Not Re-Post| Confidential

TMR
Role: ASIC CAD/EDA Flow/Methodology Developer

Work location:

Irvine/San Jose (CA)
Background and Meet and Greet: MANDATORY

Job Description:

"
• 8+ years of experience in analog/mixed-signal layout design of deep submicron CMOS circuits and at least 3+ years of recent experience on advance nodes including FinFET technologies

• Great understanding of CAD flows and tools related to ASIC/SOC methodologies

• Excellent programming skills in languages: SKILL, Perl;
Python is a plus

• Strong fundamentals in software development

• Knowledge with EMIR (RV), Physical design verification (DRC/LVS/PEX/ERC), waiver

• Working knowledge of circuit design concepts such as device characteristics, SPICE and Verilog netlists and simulation

• Excellent communication and interpersonal skills
"

Key Responsibilities:

"
• Influence tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.

• Knowledge of signoff closure - Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level

• Experience in Block-level and Full-chip integration.

• Understanding constraints and fixing design/timing techniques

• Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout

• Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area, and power requirements

• Understanding constraints and fixing design/timing techniques

• Understanding SI prevention, fixing methodology and implementation

• Proficient in Synopsys tools such ICC/ICC2, Cadence Innovus/Virtuoso

• Experience in Design Automation and UNIX system.
"

What are the Mandatory skills and skill proficiencies required for this position?
"Python (Preference:
5)
Synopsys/Cadence EDA tools/flows (Preference:
5)
TCL/Perl (Preference:
5)"

What are the Optional skills and skill proficiencies for this position?

The following details must accompany your submission:

First Name, Middle name, and Last Name:
City and State:
Open to Relocate?
Rate:
Availability:
Phone #:
Mobile #:
Email address:
Visa type:
Visa Expiration Date:
Hiring Status:

Mariana Zarate - ERM
Capgemini North America
Tel.: "

Additional Details

• Global Grade : C
• Named Job Posting? (if Yes - needs to be approved by SCSC) :
  No
• Remote work possibility :
  No
• Global Role Family : 61405 (P) Products & Systems Engineering
• Global Technical Skills Family : 60614 (T) Electrical, Electronics & Semiconductors
• Local Role Name :
  Role: ASIC CAD/EDA Flow/Methodology Developer
• Local Skills :
  Julie Skidmore
• Languages
  
  Required:
  
  :
  English