MTS, IO Design Engineering

Req  MTS, IO Design Engineering

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

We are seeking an MTS IO/Clocking Design Engineer to join our IP Design team and contribute to the development of critical high‑speed IP circuits used across Micron’s DRAM memory products. In this role you will design, develop, optimize, verify, and support these high‑speed IPs, focusing on equalization and bandwidth extension, analyzing IO impairments, clock jitter and duty cycle distortion, and assessing their impact on DRAM system timing.

• Innovate, design, optimize and verify high‑speed IO and clocking circuits used in new DRAM products.
• Apply robust high‑speed circuit design techniques and evaluate performance, including timing and jitter sensitivity of the IO data path and clock path at circuit and full‑chip level.
• Develop accurate modeling, analysis and simulation methodology to capture key circuit performance metrics and their impact on product specifications at full‑chip and system level.
• Work with Product Engineering and SI team to compare silicon performance with simulation results and support correlation activities.
• Collaborate with process integration and transistor modeling teams on Micron’s next groundbreaking process node.

• Minimum MSEE + 10 years or BSEE + 12 years of industry experience with a strong background in designing high‑speed IO interface, timing and clocking circuits with proven silicon successes.
• Ability to supervise layout work and understand good layout practices for high‑speed circuits to minimize parasitic impacts.
• Strong communication skills to convey sophisticated technical concepts to design peers, both verbally and in writing.
• Mental agility and ability to multi‑task, working with all product types (commodity, mobile, graphics) and product teams in parallel with silicon validation efforts.

• Prior experience in DRAM circuit design.
• Prior experience in channel modeling and characterization, transceiver noise and timing budget analysis, equalization techniques, SI knowledge, etc.
• Understanding of device physics and basic CMOS processing techniques.
• Demonstrated mentoring and coaching ability for early‑career engineers.
• Experience with AI/ML usage and fluency in scripting languages such as PERL or Python.

Relocation to Micron headquarters in Boise, Idaho is required for this position.

Semiconductor Design Engineer MTS

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.