Staff Engineer, APTD Backgrind/Edge Trim
Job in
Boise, Ada County, Idaho, 83701, USA
Listed on 2026-06-02
Listing for:
Micron Technology, Inc.
Full Time
position Listed on 2026-06-02
Job specializations:
-
Engineering
Process Engineer, Research Scientist, Manufacturing Engineer, Mechanical Engineer
Job Description & How to Apply Below
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Department Intro:
The Advanced Packaging Technology Development (APTD) team at Micron leads the creation of powerful memory and storage solutions that power the AI era. We work hands-on with global R&D groups, suppliers, and manufacturing teams to turn breakthrough ideas into real, production-ready technologies. We thrive on innovation and collaboration!
Position Overview:
This role will be part of a highly collaborative and innovative Advanced Packaging Wafer Edge Trim, Backgrind & Thinning R&D team, responsible for developing and scaling critical mechanical wafer processing modules.
This role offers broad opportunities for technical innovation, early stage pathfinding, and ownership of process solutions that enable next generation advanced packaging technologies. You will work closely with process integration and adjacent process areas including Bonding/De-bonding, CMP, Wet Etch, Lithography, Assembly, and Test, while driving process readiness to meet bold program, performance, and yield targets.
Responsibilities:
* Develop and optimize wafer edge trim, backgrind, and thinning processes to meet the mechanical, electrical, and reliability requirements of Micron's advanced memory products.
* Improve process capability, yield, cost efficiency, and wafer integrity through data‑driven optimization and equipment or consumable innovation.
* Conduct root‑cause and failure‑mode analyses to understand wafer damage mechanisms such as edge chipping, micro‑cracks, subsurface damage, warpage, and residual stress, and drive mitigation strategies.
* Perform fundamental research and early‑stage pathfinding to enable ultra‑thin wafer processing for next‑generation advanced packaging architectures.
* Support process transfer and ramp to production at manufacturing sites; limited domestic and/or international travel may be required.
Minimum Qualifications:
* BS or MS degree with a minimum of 4 years of experience in wafer edge trim, backgrind, wafer thinning, CMP, or mechanical wafer processing in the semiconductor industry
* Demonstrated research and development capability in science or engineering, with hands‑on experience advancing wafer processing capability through structured experimentation and learning.
* Proven expertise in experimental design (DOE), data analysis, and result interpretation, translating findings into actionable process or technology improvements.
* Strong analytical, physics‑based, and creative problem‑solving skills, applied to complex mechanical, material, and defect‑related wafer challenges.
* Ability to apply deep understanding of wafer thinning, backgrind, and edge trim processes to influence technology direction, integration strategies, and long‑term roadmap decisions.
* Proven success resolving complex process, yield, and reliability issues using root‑cause analysis, model‑based reasoning, and first‑principles understanding
* Self‑motivated and capable of working independently with minimal supervision, while consistently delivering on technical and program commitments.
* Demonstrated ability to manage numerous projects simultaneously, balancing near‑term execution with longer‑term R&D objectives.
* Strong computer proficiency, including MS Office and data visualization tools, for effective reporting and executive‑level communication.
Preferred Qualifications:
* PHD in a related field with 2+ years of relevant industry experience
* Proficiency in statistical analysis and statistical process control (SPC); experience applying statistics to variability reduction and process optimization
* Exposure to or strong interest in advanced packaging technologies such as wafer‑level packaging, bonding/de-bonding, or 2.5D/3D integration is highly desirable
* Familiarity with data science fundamentals, including Python scripting, automation, or GenAI‑enabled analysis
As a world leader in the semiconductor industry,…
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