Senior Package Design Engineer

Our vision is to transform how the world uses information to enrich life for all .Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

The Global Design, Simulation, and Substrate team at Micron Technology is a world-class group of engineers developing advanced semiconductor packaging solutions for memory products including DRAM and NAND. The team operates globally, collaborating with internal assembly sites, technology development teams, and external OSAT partners to deliver high-performance, reliable, and manufacturable package designs across Micron's product portfolio!

As a Senior Package Design Engineer, you will lead co-design activities that bridge silicon design, package architecture, and product development for advanced DRAM and memory products targeting applications such as Mobile, Automotive, Artificial Intelligence, Edge/Cloud Computing, and Data Center. During the co-design phase, you will partner with silicon design teams, Business Units, customer-facing teams, and package and product architecture teams to define and drive new product concepts from inception through High Volume Manufacturing (HVM).

Be part of the team! You will collaborate with global, multi-functional teams — including Package Architecture, Technology Development, simulation, and manufacturing — to deliver scalable, high-performance package solutions that meet electrical, mechanical, thermal, and reliability requirements.

Responsibilities Lead co-design activities by partnering with silicon design teams, Business Units, customers, customer-facing teams, and package and product architecture teams to define new product concepts, optimize die floor plans, interconnection schemes, and package architectures from the earliest stages of chip development.

Define and optimize package architectures for DRAM products, including substrate stack-up, die padlog optimization, wire bond and flip chip interconnect schemes, and BEOL/RDL flows for advanced memory packages.

Lead package layout activities — including floor planning, placement, and high-density routing — and generate and maintain design databases, package drawings, wire bond diagrams, interposer drawings, and manufacturing documentation.

Partner with electrical and simulation teams to interpret parasitic modeling and validation data, and drive design optimization and material selection decisions; conduct feasibility studies and DFM (Design for Manufacturability) reviews to assess and advance designs for performance, manufacturability, and reliability.

Partner with Signal Integrity (SI) and Power Integrity (PI) teams to incorporate simulation analysis and feedback into package architecture definition and design optimization for high-speed memory interfaces.

Collaborate with assembly engineering, internal sites, and OSAT/subcontractor partners to conduct package and DFMEA reviews, define and manage Assembly DOEs, and ensure designs meet vendor and HVM specifications.

Work with SBT (Substrate) suppliers, OSATs, Technology Development, and Package Architecture teams to define and advance design rules and routing methodologies for next-generation packaging solutions.

Support the design group's continuous improvement initiatives, including global design alignment, package design rule system development, competitive analysis, package roadmaps, and IP development.

Minimum Qualifications Master's degree in Electrical Engineering, Mechanical Engineering, Materials Science, or a related interdisciplinary field with 5+ years of industry experience in advanced memory substrate design, or Bachelor's degree in a related field with 10+ years of industry experience in advanced memory substrate design.

Hands-on proficiency with industry-standard EDA tools such as Cadence Allegro Package Designer+ / Integrity 3D-IC Platform, Siemens/Mentor Graphics Xpedition tool suite, or equivalent advanced package design tools.

Experience in advanced memory substrate design, including flip chip and wire bond interconnects, BEOL/RDL flows,…