Layout Engineer, DEG

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence.

• Build block‑level layouts in Cadence Virtuoso including floor planning, placement, routing, and optimization.
• Apply layout methods and physical constraints such as PDN, pin placement, routing blockages, and hierarchy.
• Ensure DRC, LVS, density, and reliability compliance.
• Support parasitic extraction, post‑layout verification, and ECO activities.
• Create partial custom layouts for selected device‑level or small analog blocks.

• Experience performing physical layout using Cadence Virtuoso or similar tools.
• Familiarity with DRC, LVS, physical verification, and reliability checks.
• Ability to plan, document, and review layout goals with cross‑site teams.

• Experience with DRAM, memory circuits, or large hierarchical designs.
• Background in parasitic extraction flows and post‑layout optimization.
• Hands‑on experience with partial custom layout for devices or small analog circuits.
• Strong communication skills supporting global engineering teams.

Micron offers a choice of medical, dental, and vision plans at all locations, along with paid family leave, paid time‑off, and paid holidays. Benefit programs include income protection if you are unable to work due to illness or injury. For more information, see the Benefits Guide posted on

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

To learn about your right to work .