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Engineer, Layout Engineer

Job in Boise, Ada County, Idaho, 83708, USA
Listing for: Micron
Full Time position
Listed on 2026-06-19
Job specializations:
  • Engineering
    Electronics Engineer, Hardware Engineer, Manufacturing Engineer, Automation & Mechatronics Engineer
Salary/Wage Range or Industry Benchmark: 80000 - 100000 USD Yearly USD 80000.00 100000.00 YEAR
Job Description & How to Apply Below

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Our DRAM Engineering Group drives the physical implementation behind Micron’s most advanced memory products. We work across global sites and thrive on collaboration, problem‑solving, and pushing technical boundaries. We’re looking for a Layout Engineer who will play a key role in building high‑quality physical designs for our DRAM technologies. You’ll partner closely with logic, STA, and verification teams while shaping layout strategies that balance performance, power, and area.

Your work will directly influence product success and team workflows across Micron’s global engineering community.

Responsibilities
  • Develop block‑level physical layouts using Synopsys ICC2, including floor planning, placement, routing, and optimization
  • Apply timing‑driven methods and physical constraints such as PDN, pin placement, routing blockages, and hierarchy rules
  • Ensure compliance with DRC, LVS, density, and reliability requirements
  • Support parasitic extraction, post‑layout verification, and ECO activities
  • Create partial custom layouts for selected transistor‑level or small analog blocks
Minimum Qualifications
  • Experience performing physical layout using industry EDA tools (ICC2 or equivalent)
  • Knowledge of timing‑driven layout and STA collaboration workflows
  • Familiarity with DRC, LVS, physical verification, and reliability checks
  • Ability to plan, document, and review layout goals with cross‑site teams
Preferred Qualifications
  • Experience with DRAM, memory circuits, or large‑scale hierarchical designs
  • Background in parasitic extraction flows and post‑layout optimization
  • Hands‑on experience with partial custom layout (devices, small analog blocks)
  • Strong communication skills supporting global engineering collaboration

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget.

Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on .

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

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