Process Integration Lead, APTD Boise, Idaho, Priority Posted

Position: Process Integration Lead, APTD Boise, Idaho, United States of America Company Priority Posted 3[...]
## Process Integration Lead, APTDBoise, Idaho, United States of America Apply Now Find out how well you match with this jobJob IDJR
95852
** Our vision is to transform how the world uses information to enrich life for
* all*.
** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.## Department Intro:

At Micron Technology, the Technology Development (TD) department drives innovation in memory and storage solutions. The team develops processes and technologies for next-generation semiconductor products. By collaborating with global R&D and manufacturing groups, they ensure efficient transfer and implementation of new technology nodes. Their work sustains Micron's industry leadership. Join this forward-thinking team molding the future of technology!##

Position Overview:

As a Process Integration Lead in the Advanced Packaging Technology Development (APTD) team, you will lead a team of experienced engineers developing advanced wafer level and die level interconnect technologies. You will ensure targeted products meet performance, cost, manufacturability, quality, reliability, and schedule requirements. You will also work with peers and internal partners across organizations to coordinate the transfer of new integration flows to High Volume Manufacturing (HVM) sites.

You will be recognized as an authority in broader integration areas by peers in the manufacturing and technology development organizations. The ideal team member would be adept to accepting change and volatility and operate with a sense of urgency. Apply sound engineering principles and judgment, seek advice from authorities, and make critical and timely decisions. You will need to advise and lead the work of others and ensure good communication, engagement, and accountability leading to the achievement of the program goals.##

Responsibilities:
* Drive process innovation to deliver high‐impact, scalable technology solutions.
* Define and integrate highly sophisticated, vertically aligned process flows.
* Develop innovative solutions and establish robust contingency plans.
* Define and complete the Compose of Experiments (CoE) using data-driven methodologies.
* Apply structured problem‐solving and decision‐making methods (Kempner‐Tregoe or equivalent).
* Champion cost efficiency while balancing performance, quality, and reliability.
* Communicate effectively across teams, sites, and executive leadership.
* Coach and mentor engineers and technicians while promoting a growth mindset through continuous learning and multi-functional collaboration.##

Required Experience:

* Over 10 years of professional experience within the semiconductor industry.
* MS or PhD in Electrical Engineering, Materials Science, Mechanical Engineering, Physics, Chemistry, or a closely related field, or equivalent professional experience demonstrating senior‐level technical capability.
* Professional experience in process integration, process development, advanced packaging, or closely related semiconductor technology domains within an R&D environment (IDM, foundry, OSAT, or equivalent).##

Preferred Qualifications:

We recognize that highly qualified candidates may not fulfill every criterion listed below. Candidates whose experience corresponds with most of these qualifications and who bring strong process integration and technical development leadership are encouraged to apply.
* Professional experience in process integration, process development, advanced packaging, or similar semiconductor technology areas within an R&D environment (IDM, foundry, OSAT, or equivalent).
* Proven end‐to‐end ownership of integration solutions, including technology definition, process development, qualification, and transfer to high‐volume manufacturing.
* Deep, hands‐on experience with advanced packaging and interconnect technologies, including 2.5D/3

DIC integration; wafer‐level and fan‐out packaging; and wirebond, microbump, and/or hybrid bonding.
* Proven record of direct technical ownership of solutions (hands‐on execution encouraged;…