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Layout Designer - Pathfinding

Job in Boise, Ada County, Idaho, 83708, USA
Listing for: 1000 Micron Technology, Inc.
Full Time position
Listed on 2026-07-18
Job specializations:
  • Engineering
    Electronics Engineer
Salary/Wage Range or Industry Benchmark: 130000 - 170000 USD Yearly USD 130000.00 170000.00 YEAR
Job Description & How to Apply Below
Position: Staff Layout Designer - Pathfinding

Position Overview

As a Staff Layout Designer, you will develop and prepare multi‑dimensional layouts and detailed drawings of semiconductor devices from schematics and related geometry provided by design engineers. Your role includes verifying data integrity, leading major block developments, and communicating effectively with cross‑functional teams across global sites.

Responsibilities
  • Organize and prioritize logistics and resource allocations to meet scheduled deadlines and proactively develop methodologies for issue resolution.
  • Contribute to group management and technical innovation.
  • Assign resources, schedule tasks, provide direction, and deliver quality‑controlled results.
  • Contribute to projects in a globally distributed design/layout environment.
  • Effectively mentor junior team members.
  • Improve layout efficiency through the development of automation and new methodologies.
  • Lead, plan, and deliver major blocks and product revisions.
Minimum Qualifications
  • AS or Bachelor’s degree in Electronics, Electrical Engineering, or a related field.
  • 10 years of direct experience in semiconductor layout design.
  • Deep working knowledge of EDA tools (e.g., Cadence Virtuoso, Synopsys, Calibre).
  • Strong ability to debug problems through root‑cause analysis and collaborate with engineering staff.
  • Skill in developing and applying custom layout, floor‑planning, signal‑planning, and power‑planning methodologies.
  • Strong verbal and written communication skills.
  • In‑depth understanding of design rules and high‑quality layout delivery.
  • Proficiency in physical verification analysis and debugging.
Preferred Qualifications
  • 10+ years of direct experience in semiconductor layout design.
  • BS degree in a related field.
  • Project leadership in quality optimization, die‑size shrinkage, and IC layout design with NAND, DRAM, and/or SRAM.
  • Programming skills and experience leveraging Artificial Intelligence (AI) to enhance layout workflow.
Benefits

Micron offers a comprehensive benefits program that includes medical, dental, and vision plans, income protection, paid family leave, robust paid time‑off, holidays, and additional support resources to promote wellbeing and professional growth.

Equal Opportunity Statement

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

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