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Senior IP Layout Engineer – DRAM & Analog Blocks
Job in
Boise, Ada County, Idaho, 83708, USA
Listed on 2026-07-24
Listing for:
Micron Memory Malaysia Sdn Bhd
Full Time
position Listed on 2026-07-24
Job specializations:
-
Engineering
Electronics Engineer, Hardware Engineer
Job Description & How to Apply Below
Micron Technology in Boise, Idaho, is seeking a Layout Engineer to develop IP layouts for DRAM chips and collaborate with a global team to deliver high-quality designs. This role focuses on translating circuit concepts into efficient physical layouts while maintaining tight area and performance targets.
You will verify layouts with LVS/DRC/EM, guide sub-block layouts, and contribute to project management, coordinating with US, India, Japan, and other sites to ensure on-time, successful layout
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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