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Senior​/Principal SoC Physical Design Lead; 7nm

Job in Boise, Ada County, Idaho, 83701, USA
Listing for: Celero Communications, Inc.
Full Time position
Listed on 2026-07-25
Job specializations:
  • Engineering
    Electronics Engineer, Hardware Engineer, Systems Engineer
Salary/Wage Range or Industry Benchmark: 150000 - 250000 USD Yearly USD 150000.00 250000.00 YEAR
Job Description & How to Apply Below
Position: Senior/Principal SoC Physical Design Lead (7nm+)

Celero Communications, based in Irvine, CA, seeks a Senior or Principal Physical Design Engineer to lead physical implementation of SoCs, including floor planning, CTS, P&R, and tape-out readiness.

You will collaborate with architecture, RTL, circuit, and verification teams to meet aggressive PPA targets, mentor engineers, and help define design methodologies in a fast-growing semiconductor startup.

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Position Requirements
10+ Years work experience
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