Senior RTL Design Architect - DRAM IP & Signoff
Listed on 2026-10-07
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Engineering
Hardware Engineer, Electronics Engineer, Engineering Design & Technologists, Architect / Sr. Architect -
Design & Architecture
Engineering Design & Technologists, Architect / Sr. Architect
Micron Technology in Boise, Idaho is seeking a Principal RTL Design Engineer to lead the development of high-quality DRAM digital and mixed-signal IP. You will own RTL design from architecture to silicon signoff, targeting best-in-class power, performance, and area.
Collaborate with physical design, verification, and architecture teams to meet aggressive PPA goals, drive automation, and advance RTL design methodologies while mentoring teams across global sites and delivering results.
We are looking to fill the Senior RTL Design Architect - DRAM IP & Signoff position at Micron Memory Malaysia Sdn Bhd in Boise, , United States.
Full responsibilities and requirements are described in the listing above.
Learn more about the Senior RTL Design Architect - DRAM IP & Signoff role in the description above.
We appreciate your interest in this position.
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