Debug​/Trace​/Profiling Design Engineer

Job Description

SiFive is seeking a hardware design engineer passionate about designing industry‑leading debug, trace and profiling IP to support the widespread adoption of RISC‑V as the architecture of choice for SOC designs. The engineer will lead enhancements of existing debug/trace/profiling hardware and develop new capabilities, collaborating with customers, partners, tools vendors and the RISC‑V International Association.

The focus of this position is on debug, trace, and profiling hardware. The successful applicant will address the following challenges:

• Design the best debug, trace and profiling hardware for open RISC‑V and Tile Link architectures.
• Master designing hardware as configurable generators in a domain‑specific software language for elaborating digital logic.
• Work in a fast‑paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.

• Architect, design and implement debug, trace and profiling hardware.
• Work with architecture, performance, software and hardware teams in architecture/microarchitecture exploration and specification.
• Implement RTL generators so elements self‑configure to achieve extensive configurability as a first‑class consideration.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements that enable automatic configuration/generation of documentation, verification test benches and tests, and packaged software.
• Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
• Ensure knowledge is shared via creation and maintenance of great documentation and participation in a collaborative design culture.

• Knowledgeable in debug, trace and profiling architecture and concepts.
• Knowledgeable in debug interfaces, JTAG and cJTAG.
• Knowledgeable in CPU architectures, power management and SoC design.
• Experience with debugging tools and profiling methods.
• Proficiency with hardware (RTL) design in Verilog, System Verilog or VHDL.
• Attention to detail and a focus on high‑quality design.
• Ability to work well with others and a belief that engineering is a team sport.
• Knowledge of at least one object‑oriented and/or functional programming language.
• Knowledge of Chisel/Scala, RISC‑V architecture, Git/Jira/Confluence is a plus.
• 7+ years of industry experience leading and directly contributing to architecture, microarchitecture and RTL design for debug/trace/profiling hardware for high‑performance processors.
• MS or PhD in EE, CE, CS or a related technical discipline.

This position requires successful background and reference checks and satisfactory proof of your right to work in France. Employment is contingent upon verifying that employees are authorized for access to export‑controlled technology under applicable export control laws or that the company can obtain necessary export licenses or other approvals.

SiFive is an equal opportunity employer. SiFive celebrates diversity and is committed to creating an inclusive environment for all employees.