Senior SoC Subsystem and I​/O Architect - LPU

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world.

Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

We are seeking a Senior SoC Subsystem & I/O Architect to join our ambitious LPU team. This role involves establishing the high-level architecture for next-generation AI and high-performance computing products. The role requires extensive architectural expertise across SoC subsystems and uncore IPs including PCIe/CXL, NVLink/NVLink-C2C, UCIe, AXI/CHI, NoC fabrics, memory systems, coherency, boot, system initialization, protection mechanisms, reliability, availability, serviceability, power management, debug, firmware interfaces, and platform initialization.

If you are prepared to make a difference and be part of a dedicated team, this is your opportunity!

• Define high-level SoC subsystem architecture for LPU products.
• Convert LPU product requirements into architectural specifications for uncore, IO, memory, firmware-facing, boot, reset, safety, fault tolerance, diagnostic, and power regulation subsystems.
• Collaborate intimately with IP teams to develop detailed build documents for PCIe/CXL, NVLink/NVLink-C2C, UCIe, AXI/CHI, NoC fabrics, memory controllers, coherency blocks, MMUs/IOMMUs, boot, reset, and associated SoC infrastructure.
• Specify subsystem behavior encompassing enumeration, capability discovery, configuration flows, sequence control of memory operations, data consistency, address mapping, interrupt handling, virtualization, error handling, and firmware/software-visible controls.
• Build or guide functional and architectural models from specifications, using C++, SystemC, Python, or similar languages.
• Use models to validate architecture intent, subsystem behavior, configuration sequences, and IP interactions before RTL or silicon is available.
• Drive tradeoffs across bandwidth, latency, power, area, timing, scalability, reliability, security, debuggability, and software usability.
• Review IP specifications, subsystem architecture documents, model behavior, verification plans, and validation strategies.
• Collaborate with architecture, IP, firmware, software, RTL, verification, platform, and post-silicon teams to bring architecture decisions to completion.

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
• 8+ years of proven experience in SoC architecture, subsystem architecture, IO architecture, interconnect architecture, GPU/CPU architecture, accelerator architecture, or high-performance systems.
• Strong understanding of SoC architecture and uncore subsystem development.
• Extensive understanding of IO and interconnect cores including PCIe, CXL, NVLink, NVLink-C2C, UCIe, AXI, CHI, or NoC fabrics.
• Experience working from product requirements to architecture requirements and IP/subsystem specifications.
• Experience crafting functional models, architectural models, golden models, or C/SystemC models from architecture specifications.
• Solid grasp of memory ordering, coherency, address translation, interrupts, virtualization, MMUs/IOMMUs, enumeration, configuration, and error management.
• Solid knowledge of boot, reset, firmware handoff, capability discovery, security, RAS, debug, and power-management architecture.
• Strong communication abilities and capability to harmonize architecture decisions across IP, firmware, software, verification, and product groups.

• Hands‑on experience with LPU, GPU, CPU, AI accelerator, chiplet, or multi‑die SoC architecture.
• Extensive knowledge in PCIe/CXL, NVLink/NVLink-C2C,…