Head of Design Engineering; Silicon

SBT is the exclusive executive recruiting firm for this confidential position.

This confidential startup company is a well-funded, high-growth AI hardware innovator building next-generation SoC solutions for high-performance applications. Backed by significant institutional investment, the company is rapidly expanding its leadership design team to drive multiple advanced-node tape-outs. With a focus on execution excellence and scalable silicon development, the organization is assembling a world-class engineering team to deliver complex, high-performance products.

• Own SoC execution from RTL → GDSII: drive end-to-end implementation planning, quality, and schedule from synthesis through place & route and full-chip closure to tape-out
• Lead silicon bring-up readiness and post-silicon feedback: partner with validation, firmware, and system teams to ensure strong design-for-debug and observability
• Provide hands‑on technical leadership across physical implementation, including floor planning, CTS, STA/timing closure, power/clock distribution, SI/PI analysis, and reliability at advanced nodes
• Serve as the technical owner for high‑speed interconnect integration, specifically PCIe and CXL
  : partner with PHY, controller, and IP teams to ensure protocol compliance, performance targets, and seamless integration at the SoC and system level
• Build and scale a high‑performing silicon engineering team: hire, mentor, and establish execution rigor across multiple concurrent programs
• Drive cross‑functional alignment with architecture, system, and software teams to ensure PCIe/CXL subsystems meet bandwidth, latency, and coherency requirements

• 10+ years in SoC/ASIC development roles with multiple successful tape‑outs, including ownership through full chip lifecycle
• Deep expertise in PCIe and/or CXL architectures
  , including controller/PHY integration, protocol compliance, and system‑level performance optimization
• Strong experience with high‑speed interface integration, timing closure, and SI/PI considerations at advanced process nodes
• Proven ability to operate effectively in fast‑paced startup environments, with experience building processes, managing ambiguity, and scaling teams
• Demonstrated leadership experience managing and developing high‑performing engineering teams in complex silicon programs