Senior ASIC Design Engineer

Senior ASIC Design Engineer

We are seeking a highly skilled Senior ASIC Design Engineer to lead the design and development of advanced ASIC solutions. The ideal candidate will have a strong background in ASIC design and a passion for innovation in silicon architecture, particularly in AI datacenter applications.

Key Responsibilities

• Lead the design and development of complex ASIC projects from concept to production.
• Develop RTL code using Verilog and System Verilog for various components including Microarchitecture and SOC designs.
• Collaborate with cross-functional teams to define requirements and deliver optimized designs that meet product specifications.
• Perform extensive verification and validation of designs to ensure high-quality outputs and compliance with standards.
• Engage in IP design and integration, focusing on Ethernet, UCIe, UALink, and HBM technologies.
• Contribute to the architecture and design of memory subsystems and cache coherence mechanisms.
• Mentor junior engineers and provide technical guidance on best practices in ASIC design.

Qualifications

• Bachelor's (Master's or PhD preferred) in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of experience in ASIC design and development.
• Proficient in RTL design using Verilog and System Verilog.
• Strong understanding of Microarchitecture, SOC design, and IP design practices.
• Experience with Ethernet, UCIe, PCIe, UALink, and HBM technologies.
• Familiarity with silicon architecture concepts, particularly in AI datacenter applications.
• Knowledge of memory subsystem design and cache coherence strategies.

Benefits

• Competitive salary commensurate with experience including base salary, performance-based bonus, and early-stage equity grant
• Comprehensive benefits including health, dental, vision, and life insurance
• Well-equipped, sunny offices in Santa Clara, CA and Boston, MA
• Relocation assistance and visa sponsorship
• Perks include a daily lunch stipend, 401k match, and more
• A collaborative, continuous-learning work environment with smart, dedicated colleagues engaged in developing the next generation of architecture for high-performance computing