Design Verification Engineer – Coherent Interconnect; CHI

About Si Five As  the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer.

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Job Description:

The Role Si Five  is looking for a Staff Design Verification Engineer to drive verification of a next-generation cache-coherent interconnect subsystem with a strong focus on CHI-based architecture and protocol  this role, you will own complex verification problems spanning coherent data movement, protocol correctness, ordering, snoop and home-node interactions, credit- and flow-control behavior, and subsystem integration across multiple interface boundaries. This is a horizontal role with broad impact across the coherent interconnect space, requiring strong technical judgment, deep debug ability, and the ability to influence verification strategy beyond an individually assigned block.

This is a Staff Engineer individual-contributor role. We are looking for someone who can define verification strategy, identify architectural and verification gaps early, solve difficult protocol and integration problems, and raise the overall quality bar for the broader interconnect verification effort.

Responsibilities Drive verification of CHI transactions across request, response, snoop, and data paths, including corner cases involving concurrency, hazards, deadlock avoidance, and ordering

Develop and maintain robust verification environments, protocol checkers, scoreboards, stimulus, and coverage models for coherent traffic, ordering rules, retries, back pressure, flow control, and error handling

Verify integration behavior across caches, home nodes, request nodes, snoop filters, bridges, and protocol-adaptation paths

Define high-value directed and constrained-random scenarios that expose corner cases in coherency, credits, buffering, arbitration, and system-level interactions

Partner closely with architecture, design, formal, and software teams to clarify requirements, close ambiguities early, and accelerate debug and signoff

Analyze failures efficiently, isolate root cause, and drive durable fixes across RTL, assertions, testbench infrastructure, and test content

Improve methodology, infrastructure, and debug productivity for the broader coherent interconnect verification effort

Contribute to review quality across specifications, verification plans, coverage closure, and debug strategy

Mentor other engineers through technical leadership, design reviews, and verification best practices

Minimum Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related…