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Sr. Design Verification Engineer - QGOV

Job in Boulder, Boulder County, Colorado, 80301, USA
Listing for: Nutanix
Full Time position
Listed on 2026-06-27
Job specializations:
  • Engineering
    Test Engineer
Salary/Wage Range or Industry Benchmark: 147600 - 246000 USD Yearly USD 147600.00 246000.00 YEAR
Job Description & How to Apply Below
Position: Staff/ Sr. Staff Design Verification Engineer - QGOV
Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group  ASICS Engineering General

Summary:

Design Verification Role:

Familiarity with RTL design in Verilog and System Verilog Develop verification methodology, ensuring scalable and portable environment across simulation and emulation.

Develop test plan to verify Hardware building blocks, Design macros and Standard interfaces (PCIE, DDR, USB, I2C, SPI, etc) .Own end to end DV tasks from coding Test bench and test cases, write assertions, running simulations and achieving all coverage goals

Explore innovative DV methodologies (formal, simulation and emulation based) to continuously push the quality and efficiency of test benches

Develop verification methodology, ensuring scalable and portable environment across simulation and emulation.

Develop and maintain emulation environment to collect metrics related to emulation environment.
** Need to be in San Diego full time, 5 days a week Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information.
** Must be a U.S. citizen and eligible to receive a U.S. Government security clearance
*
* Required Qualifications:

5+ years of work experience with RTL/FPGA design (Verilog), embedded system architecture5+ years of Design Verification, Emulation and Debug experience with simulation and emulation and prototyping flows

Relevant experience of 5+ yrs in any of the mentioned domain - Design/Verification/ Implementation

Preferred Qualifications:

One or more of the following preferred:

Knowledge of communication protocols such as AXI4-x, DDRx, PCIe, etc.

Strong System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodology

Good understanding of chip-level functional model building

Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System CKnowledge of Behavioral and Structural models and familiarity with simulation environments

Experience customizing and debugging make-based build flows and working with Xilinx’s Vivado tools

Experience with cm tools such as Git and Gerrit.

Experience in formal / static verification methodologies will be a plus

Experience with emulation platforms – Palladium, Zebu, Veloce, FPGAs.

Experience with synthesizing and optimizing designs and verification components developed in synthesizable Verilog.

Experience with C/C++ DPI transactors and monitors.

Develop and maintain emulation environment to collect metrics related to emulation environment.

Develop environment to run verification test cases, OS boot, performance benchmarks and other vectors.

Design, develop, and maintain CAD infrastructure for silicon design teams enabling bring up, test and debug automations.

Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures.

Experience with debugging tools such as JTAG and lab test equipment such as logic analyzers, oscilloscopes, signal generators, etc.

Experience with GLS, and scripting languages such as Perl, Python is a plus Linux OS proficiency

The ideal candidate would be a self-starter with strong initiative, discipline, motivation, and a focus on quality.

The candidate must be a team player and be flexible and open to a variety of task assignments within the team.

Minimum Qualifications:

Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.

ORMaster's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.

ORPhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disabili or call Qualcomm's toll-free…
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