Digital Verification Manager

About OLIX

AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade.

The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.

We’re searching for an ASIC Digital Verification Manager to lead and deliver functional verification of the digital subsystems of our next-generation high-speed mixed-signal ASICs. This is a hands-on leadership role with a strong focus on execution speed, first-silicon success, people management, and cross-functional alignment. You will drive your team to verify complex digital systems that integrate high-bandwidth interfaces, deterministic control loops, and advanced mixed-signal blocks—on schedule, on budget, and with uncompromising quality.

As both a leader and technical authority, you will mentor engineers, set a high bar for verification rigor, and ensure the program executes with precision from spec through tape-out sign-off to silicon bring-up and mass production.

This is a rare opportunity to own end-to-end verification leadership on next-generation high-speed mixed-signal ASICs — from architecture through first silicon to mass production — with real authority over strategy, talent, and technical direction. If you thrive at the intersection of rigorous verification discipline and high-stakes execution speed, this role puts you at the centre of the hardest, most consequential problems in modern ASIC development.

• Execution Ownership & Speed – Lead end-to-end verification of digital subsystems (testbench architecture, UVM development, functional and code coverage closure, formal verification, CDC/RDC sign-off, low-power verification, gate-level simulation, and emulation/FPGA prototyping), ensuring aggressive schedule targets are met without compromising quality.

• Right-First-Time Delivery – Define and enforce verification plans, sign-off criteria, and silicon-correlation strategies that catch bugs pre-silicon and drive first-silicon success.

• Line & Performance Management – Manage, mentor, and grow a high-performing, multi-site team of 6–12 verification engineers. Own goal-setting, performance reviews, career development, and hiring across sites, while fostering a culture of accountability, collaboration, and continuous improvement that holds up across time zones.

• Cross-Functional Alignment – Drive seamless collaboration with design, architecture, analog, DFT, firmware, post-silicon validation, and test teams to keep programs moving fast and aligned from spec → vplan → implementation → sign-off → bring-up.

• Program Leadership – Define and track aggressive verification schedules, compute and license resource plans, and risk-mitigation strategies. Communicate progress, coverage status, trade-offs, and escalation paths clearly to executives and customers.

• Technical Direction – Provide architectural guidance for verification environments targeting high-speed digital subsystems, including multi-lane data paths, clocking and reset schemes, and mixed-signal control loops (real-number modeling and AMS co-simulation).

• Culture of Speed & Quality – Champion verification automation, reusable UVM components, regression and triage infrastructure, streamlined methodologies, and knowledge sharing to deliver high-quality silicon on tight timelines.

• 10+ years of digital ASIC verification, with at least 3 full product cycles successfully executed from specification to high-volume production.

• Proven track record of driving on-time, first-silicon success on complex, high-performance ASICs with mixed-signal interfaces (e.g., Ser Des, DACs/ADCs, RF SoCs, display/camera pipelines).

• Strong…