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Senior Product Manager, Hardware – NPU IP

Job in Burlingame, San Mateo County, California, 94012, USA
Listing for: Jobtailor
Full Time position
Listed on 2026-08-02
Job specializations:
  • IT/Tech
    Hardware Engineer
Salary/Wage Range or Industry Benchmark: 140000 - 190000 USD Yearly USD 140000.00 190000.00 YEAR
Job Description & How to Apply Below

Responsibilities

  • Hardware roadmap. Translate customer requirements, competitive pressure, and architectural constraints into a track-by-track feature list with explicit gating — what ships, what slips, what gets cut.
  • Architecture freeze. Build the case for contested architecture decisions (e.g., dedicated requant unit vs. wider MAC array), run the tradeoff with the architects, and bring a recommendation to the PSC.
  • Customer engagement. Named hardware product owner for anchor accounts. Present new features, ingest formal architecture feedback, and convert it into roadmap input.
  • IP usability. Find what customers are silently working around — API wrappers, glue logic, custom RTL hooks, workaround scripts.
  • Hardware competitive intelligence. Track Synopsys NPX6, Arm Ethos‑U85, Ceva Neu Pro‑M, Veri Silicon Vivante, and NVIDIA Jetson at the architectural level. Translate competitor moves into specific feature requirements before gaps appear in customer evals.
  • SoC integration positioning. Decide which integration knobs (AXI4/ACE‑Lite, Core Sight, power‑domain partitioning, performance counters) are exposed, which are productized, and how they’re described in the integration guide.
  • Functional safety positioning. Sequence FMEDA work, lockstep configurations, and safety‑island architecture.
Requirements
  • 5–8 years of PM experience on hardware or silicon products. Senior IC background.
  • Customer‑facing track record
    - You have run architecture reviews with sophisticated technical buyers — Tier 1 automotive, OEM SoC teams.
  • IP‑licensing rhythm
    - Customers integrate our IP for 18–24 months before silicon ships. Decisions today appear in production volume in 2028.
  • Agent‑pilled
    - You use agentic AI tools daily (Claude Code, Cursor, or equivalent) to produce work.
  • Customer first.
  • Direct experience with at least two of: NPU/AI accelerator architecture, SoC integration, DSP/vector compute, automotive silicon, semiconductor IP licensing.
  • EE/CE/CS engineering degree or equivalent depth.
  • Experience with in‑person technical customer reviews.
  • Bay Area resident or willing to relocate to Burlingame.
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Position Requirements
10+ Years work experience
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