Deep Learning Compiler Engineer; New Grad

Quadric has created an innovative software-driven AI inference processor. Licensed as IP, the architecture is targeted to run neural network (NN) inference workloads in a wide variety of edge and endpoint devices, ranging from battery-operated smart-sensor systems to high-performance automotive or autonomous vehicle systems. Unlike other neural engines in the industry today that can only accelerate a portion of a machine learning graph, the Quadric GPNPU executes both NN graph code and conventional C++ DSP and control code.

As a new-grad Deep Learning Compiler Engineer, you will work on CGC, Quadric's neural network compiler that lowers ONNX models through Relay IR down to C++ targeting the Chimera GPNPU. You will own work in real compiler passes—layout selection, memory allocation, operator splitting, code generation—and your changes will ship into the code that runs on Quadric silicon. This is a hands‑on engineering role on a small, senior team.

You will design IR transformations, debug the C++ the compiler emits, and drive how efficiently neural networks map to our hardware. The ramp is steep, the codebase is large, and the feedback loop from your changes to running silicon is short.

Note:

We strongly prefer candidates located in the California Bay Area, or willing to relocate to the California Bay Area and regularly collaborate from our Burlingame office.

From time to time, the team and company gather for onsite meetings and off‑site events. These in‑person moments are an important part of how we build relationships, collaborate effectively, and align on priorities, and participation is expected for all team members.

• Own compiler passes. Design and implement IR transformations that lower neural network IR to GPNPU‑targeted code. Take pieces of the pipeline as yours and maintain them.
• Debug end‑to‑end. Diagnose compilation issues by tracing problems from generated C++ back through the pipeline. Use IR dumps, static analyses, and the ISS to root‑cause compilation failures and performance regressions.
• Improve compiler decisions. Work with senior engineers to reduce data movement, improve core utilization, and tighten the gap between what the hardware can do and what we currently emit.
• Collaborate across teams. Partner with the kernel, hardware, and data science teams to align compiler features with real model requirements and hardware constraints.
• Strengthen the toolchain. Contribute to test infrastructure, debugging utilities, and developer ergonomics across the CGC pipeline and runtime.

• Bachelor's, Master's, or PhD in Computer Science, Electrical Engineering, or a related field, completed within the past year (or completing within the next six months).
• Strong proficiency in Python and C++.
• Solid grasp of compiler concepts: intermediate representations, dataflow analysis, transformation passes, and lowering.
• Comfort reading and reasoning about large, unfamiliar codebases.
• Strong debugging and problem‑solving skills, with the ability to communicate findings clearly in writing and review.

• Coursework, research, or significant project experience in compilers, program analysis, or domain‑specific languages.
• Hands‑on exposure to ML compiler frameworks such as TVM, MLIR, XLA, Glow, or IREE — bonus if you have written a non‑trivial pass.
• Familiarity with neural network quantization, fixed‑point arithmetic, or numerical analysis for ML.
• Experience with hardware‑aware code generation for accelerators (GPU, DSP, NPU).
• Some exposure to assembly, instruction scheduling, or low‑level code generation.
• Prior internship experience in compilers, ML systems, or performance engineering.
• Published research or open‑source contributions in compilers or ML systems.

• Competitive salary and meaningful equity.
• Medical, dental, and vision plan options starting on day one.
• 401(k) retirement plan.
• Flexible paid time off (unlimited, non‑accrual) to support work‑life balance.
• Company‑provided lunches and a stocked kitchen when working in‑office.
• Convenient office location within walking distance of the Caltrain station.
• Support for commuting, including monthly parking or…