FIP Layout Engineer
Job in
Burlington, Chittenden County, Vermont, 05401, USA
Listed on 2026-06-27
Listing for:
Intersources
Full Time
position Listed on 2026-06-27
Job specializations:
-
Engineering
Telecoms Engineering, Electrical Engineering, Electronics Engineer
Job Description & How to Apply Below
FIP Layout Engineer
Job Location:
Burlington, VT
Working on TSMC 5nm and 3nm projects for the duration of 1 year.
Looking for experienced layout designers for contract position:
- With strong finfet experience in 5nm or 3nm TSMC.
- With highspeed Ser Des or equivalent analog layout experience.
- That can take direction effectively from project layout lead, layout macro owner, and circuit designers.
- Must be experienced with and use Virtuoso XL for 1to1 schematic to layout correspondence.
- That works independently once given a set of requirements and will ask questions when unsure of tradeoff decision.
- That effectively communicates with layout lead, layout macro owner, and circuit designers of any observed and anticipated potential issues with the design and communicating them when uncovered.
To View & Apply for jobs on this site that accept applications from your location or country, tap the button below to make a Search.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
Search for further Jobs Here:
×