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Senior ASIC Design Engineer – Low-Power CMOS & Tape-Outs
Job in
Cambridge, Middlesex County, Massachusetts, 02140, USA
Listed on 2026-07-13
Listing for:
The Charles Stark Draper Laboratory, Inc.
Full Time
position Listed on 2026-07-13
Job specializations:
-
Engineering
Hardware Engineer, Electronics Engineer, Test Engineer
Job Description & How to Apply Below
The Charles Stark Draper Laboratory, Inc. in Cambridge, MA seeks an experienced ASIC hardware engineer to design and simulate transistor‑level circuits and contribute to system‑level architectures.
You will lead multi‑disciplinary teams, optimize for performance, power, and cost, and drive complex design challenges from requirements through tape‑out. Requires 7–10 years (or 5–10 with a master’s) in ASIC hardware engineering, fluent System Verilog/Verilog/VHDL, and experience with Cadence or
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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