Server CPU Clock Physical Design Engineer, level - Cambridge, UK

Position: Server CPU Clock Physical Design Engineer, Staff level - Cambridge, UK
Company:

Qualcomm Technologies International Ltd Job Area:

Engineering Group, Engineering Group  ASICS Engineering General

Summary:

Job Overview Qualcomm is seeking an experienced CPU Clock Physical Design Engineer to join the Nuvia Data Center CPU team in Cambridge, UK . The team is developing next-generation, high-performance, power-efficient custom CPU technology for advanced compute and server-class platforms that will help transform the  this role, you will help define, implement, and optimize best-in-class clock generation and distribution solutions for high-frequency CPU designs.

You will work closely with microarchitecture, RTL design, CAD, circuit design, block-level physical design, and top-level physical design teams to deliver robust, low-skew, low-power clocking solutions for next-generation CPUs.This is a high-impact technical role for engineers who enjoy solving complex clocking, timing, power, and implementation challenges. You will have the opportunity to influence CPU clocking architecture and methodology from early design planning through physical implementation, signoff, and silicon correlation.

This position is open for Staff Engineer level, with scope, ownership, and technical leadership scaled according to experience.

Key Responsibilities will include

As a Server CPU Clock Physical Design Engineer , you will:

Define and drive the overall clock generation and clock distribution methodology for next-generation data center CPU designs.

Work with microarchitecture, RTL, CAD, circuit, block-level physical design, and top-level physical design teams to understand, implement, and validate CPU clocking requirements.

Architect, implement, and optimize low-skew, low-power clock networks using approaches such as clock H-trees, clock mesh, clock spines clocking methodologies

Partner with CAD and physical design teams to develop and deploy clocking techniques that optimize skew, latency, clock power, timing margin, routability, and design convergence.

Use SPICE simulation and circuit-level analysis to validate clock circuits, clock paths, and electrical behaviour across process, voltage, and temperature conditions.

Analyse and debug clock-related timing, power, noise, variation, and physical implementation issues across multiple modes, corners, and operating conditions.

Provide feedback and guidance to block-level and top-level physical design engineers on required clocking fixes, optimization opportunities, and signoff risks.

Collaborate with PLL, timing, power, CAD, and implementation teams to align clock source assumptions, jitter budgets, clock uncertainty, and signoff methodology.

Develop, document, and improve clock construction, analysis, and validation flows for future CPU generations.

For Staff-level candidates, provide technical leadership, mentor engineers, influence cross-functional methodology, and drive resolution of critical clocking challenges.

Required Skills and Experience We are looking for candidates with strong experience in CPU clocking, physical design, timing, and circuit-aware implementation .The ideal candidate will have:

Strong experience in the construction and analysis of low-skew and low-power clock generation and distribution networks .Hands-on experience with clock distribution structures and methodologies such as Clock H-tree, Clock Mesh, Clock Spines Strong understanding of CTS, clock balancing, insertion delay, skew optimization, useful skew, clock power reduction, and clock latency trade-offs.

Good understanding of device physics, RC delay, signal integrity, variation, and electrical effects that influence clock quality and timing robustness.

Proficiency in SPICE simulation and analysis for circuit design, clock-path validation, and electrical verification.

Strong understanding of static timing analysis and the interaction between clock architecture, timing closure, jitter, uncertainty, OCV/AOCV/POCV, setup/hold closure, and signoff quality.

Ability to debug complex clocking issues across implementation, timing, power, noise, variation, and circuit domains.

Experience working with industry-standard EDA implementation and signoff flows for physical design, timing…