UVM Digital Verification Engineer

Overview:

Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 2,000+ employees of Draper tackle important national challenges with a promise of delivering successful and usable solutions. From military defense and space exploration to biomedical engineering, lives often depend on the solutions we provide. Our multidisciplinary teams of engineers and scientists work in a collaborative environment that inspires the cross-fertilization of ideas necessary for true innovation.

For more information about Draper, visit  Description

Summary:

Draper’s Digital Design Team is seeking a motivated and experienced UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern verification strategies to complex digital and mixed-signal designs in the areas of embedded security, cryptography, signal and image processing, navigation and communications.

Job Description:

Duties/Responsibilities Design and simulate circuits at transistor-level to implement architecture and requirement specifications

Contribute to system-level design

Optimize hardware designs for performance, power, and cost Evaluate the hardware feasibility of complex algorithms and requirements

Contribute to complex chip architectures and designs

Contribute to efforts to drive solutions to complex problems - develop requirements, propose ways forward when customer requirements are unclear or incomplete, and adapt appropriately to changes in requirements

Perform or guide physical layout, including floor-planning, and simulate circuits using extracted parasitics.

Perform other duties as assigned

Skills/Abilities Proficiency in integrated circuit design

Understanding of integrated circuits, semiconductors, and general computer architecture

Ability to write detailed design specifications

Excellent verbal and written communication skills

Excellent mathematical skills

Excellent organizational skills and attention to detail

Excellent time management skills with the proven ability to meet deadlines

Strong analytical and problem-solving skills

Ability to prioritize tasks

Demonstrate strong organization, planning, and time management skills to achieve program goals

Education

Requires a bachelor's degree in Engineering, or related field. Masters degree preferred.

Experience Requires 3-5 years of experience with a bachelor's degree, or 0-2 years of experience with a master's degree in Integrated Circuits or ASIC Hardware Engineering or related.

Additional

Job Description:

You will develop verification approaches, author and execute verification plans, and use formal analysis tools. You will work in multi-disciplinary teams with opportunities to learn, grow and contribute to a variety of projects. Join us as we develop the next generation of digital and embedded hardware platforms.

Develop verification and test plans

Develop UVM Agents for proprietary buses

Instantiate VIPs for industry standard buses

Work in both block-level/chip-level UVM testbench environment

Work with RTL designers to resolve simulation issues

Implement cover groups according to design requirements

Work on code and functional coverage closures to achieve 100%
Perform code reviews and to mentor junior engineers in the group

Fluent in System Verilog including SVARecent experience with UVM/UVMFFamiliarity with at least one major industry simulator (Questasim, Xcelium, VCS)
Familiarity with at least one IEEE bus standard.

Experience with DDR3/DDR4, Amba Axi protocols

Firm grasp of constrained-random testing and coverage-driven verification

Experience with formal analysis

Practice using Python, Perl, Bash or other scripting languages

Ability to work in a Linux environment

Strong analysis and…