Fpga​/Asic Design Engineer

Position: (US CITIZEN ONLY) FPGA/ASIC Design Engineer
Job Title: FPGA/ASIC Design Engineer
Location: 1 Federal Street, Camden, NJ
Work Schedule: 9/80 (Every other Friday off), 8:00 AM Start
Employment Type: Full-Time | Onsite
Citizenship Requirement: U.S. Citizenship Required

About the Role

We are seeking a mid to senior-level FPGA/ASIC Design Engineer to contribute to the architecture, design, implementation, and validation of high-performance systems supporting critical national security missions. You will work on cutting-edge FPGA and ASIC technologies involving complex algorithms, high-speed protocols, and cryptographic logic.

This role provides high visibility and impact within our engineering teams, focused on developing secure, robust communication systems for defense applications.

Key Responsibilities

• Architect, implement, and verify complex digital designs using VHDL targeting FPGAs and/or ASICs.
• Integrate and validate cryptographic algorithms and high-speed protocol interfaces including NVMe
  , PCIe/SRIOV
  , 10G-400G Ethernet
  , and TCP/IP
  .
• Develop and execute System Verilog UVM test benches and assertions for simulation and verification.
• Perform SW-driven validation using C++ on SOC evaluation boards (e.g.,
  Xilinx MPSoC
  ) running Linux.
• Contribute to the end-to-end development lifecycle
  , from RTL design through synthesis, static timing analysis (STA), and lab bring-up.
• Collaborate closely with cross-functional teams including software, systems, and verification engineers.
• Use industry-standard EDA tools (e.g.,
  Synopsys DC/Primetime
  , Vivado
  , Mentor Questa
  , Catapult HLS
  ).

Basic Qualifications

• Bachelor's degree in Electrical Engineering
  , Computer Engineering
  , or related field (
  Master's preferred
  ).
• 3+ years of hands-on experience in FPGA/ASIC development with VHDL and Xilinx FPGA/Vivado
  .
• Proven experience in full design lifecycle:
  architecture
  , RTL coding
  , verification
  , synthesis
  , and timing analysis
  .
• Strong debugging, problem-solving, and analytical skills.
• Excellent written, verbal, and presentation communication abilities.

Preferred Qualifications

• Experience with High-Level Synthesis (HLS) tools and methodologies.
• Proficiency in C++ (OOP) for embedded software and driver development.
• Familiarity with System Verilog Assertions (SVA) and UVM verification
  .
• Prior work with high-speed digital protocols (e.g.,
  PCIe
  , Ethernet
  , TCP/IP
  ) beyond just IP instantiation.
• Exposure to Mentor EDA tools
  : CDC, Lint, RDC, and Advanced Clocking techniques.
• Experience in defense, aerospace, or communications domains
  .

Tools & Technologies Used

• Languages/Tools: VHDL, C++, System Verilog, UVM, SVA
• EDA Tools: Vivado, Synplify, Mentor Questa, Synopsys DC/Primetime, Catapult (HLS)
• Platforms: Xilinx MPSoC, Linux
• Protocols: PCIe, Ethernet, TCP/IP, NVMe

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