FPGA​/ASIC Design Engineer

Job #: 146223

Title:

FPGA/ASIC Design Engineer

Location:

Camden, NJ Salary Range: 90.00 Position: FPGA

Description:

ENG
- The FPGA/ASIC Design Engineer is responsible for the architecture, implementation, and verification and validation through software integration testing for complex FPGA and/or ASIC systems supporting communication products for national security. This role develops high-throughput designs involving cryptographic algorithms and high-speed protocols while performing simulation, validation, and debugging activities on system-on-chip FPGA platforms. The position also utilizes advanced electronic design automation flows and tools to support design development, testing, and integration.

Requirements:
#Job Details

* Facility Type:
Engineering / Systems Support

* Aircraft Worked:
DoD/Military

* Job Duration:
Contract

* Schedule:

All Shifts

* Tools:
Not Required

* Pay Rate:
Not Available

#Education & Job Requirements

* Bachelor of Science in Electrical Engineering or Computer Science, or equivalent.

* A minimum of 3 years of experience with a proven track record of implementing complex algorithms targeting ASICs and FPGAs.

* Proficient in VHDL with over 5 years of experience , including Xilinx FPGA design using Vivado EDA tools .

* Experience using Mentor EDA tools for CDC (Clock Domain Crossing), linting, AC (Auto Check), and RDC (Reset Domain Crossing) analysis .
* Excellent analytical and debugging skills.

* Good verbal, written, and presentation skills.

* U.S. Citizenship required.

#Professional Attributes

* Strong analytical mindset for troubleshooting and debugging complex systems.

* Effective communication skills for collaboration and technical discussions.

#Preferred Skills

* Hands-on experience completing multiple complex designs, including architecture, design, verification, synthesis, and static timing analysis (STA) . Experience in this area is considered a strong plus.

* Master's degree in Electrical Engineering or Computer Science preferred.

* High Level Synthesis (HLS) with Vivado.

* Embedded software development in C++ using object-oriented programming.

* System Verilog Assertions (SVA).

* Knowledge of high-speed protocols, including PCIe, TCP/IP, and Ethernet, beyond simply instantiating IP cores, is a strong plus.

#Job Duties & Functions

* Develop architectures for implementation of high-throughput complex designs involving cryptographic algorithms using VHDL with high-speed protocols including NVMe, PCIe/SRIOV, 10G-400G Ethernet, TCP/IP, and IP development and integration targeting ARM SoC FPGAs and/or ASICs.

* Write and debug tests and sequences for end-to-end simulation using the UVM framework and System Verilog Assertions.

* Write and debug C++-based software-driven validation on SoC evaluation boards running Linux.

* Utilize electronic design automation tools and methodologies including Synopsys DC, Primetime, Synplify, Xilinx, Intel, Microchip EDA tools, High Level Synthesis, Mentor Questa family, UVM VIPs, Clock Domain Crossing tools, and Catapult HLS.

#Team Global Benefits

* Medical, Dental, Vision, 401 (k), and more!

* TG Rewards Program

* Employee Referral Program

Job Type: Temporary Post Date: 03/06/2026