ASIC​/FPGA Design Engineer; SMES

ASIC/FPGA Design Engineer (SMES)

Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed crypto applications. S/he will architect, implement high speed crypto architectures, on ASICs/Xilinx Zynq/MPSOC class FPGAs, with hands on design/debug with Ethernet, TCP/IP protocols.

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Harris has state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA with HLS, Mentor EDA Family suite :
Questa, VIPs, UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, and Catapult (HLS). This is a key, high impact role in the organization to ensure robust quality and delivery of communication products for National Security.

Essential Functions:

• Responsible for deriving engineering specifications from system requirements and developing detailed architecture
• Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint)
• Generate test plans
• Perform module level verification, synthesis/STA, Lab debug, SW driven validation on Linux based SOC evaluation boards
• Silicon/FPGA bring up, characterization and production ramp/support/collateral

Qualifications:

• BSEE, MSEE Preferred.
• 5+ year's equivalent experience developing, implementing, and verification of high-performance communications/networking ASIC/FPGA products.
• Experience mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware and architecture/system design tradeoffs.
• Proficient with CDC, RDC. Formal EDA.
• Proficient in VHDL.
• Proficient with Synthesis/PAR: SDC, Synopsys Synplify, Vivado
• Strong logic/board debug, and analytical skills.
• Experience with project leadership and EVM
• Excellent written, verbal, and presentation skills.
• Active SECRET Clearance

Preferred Additional

Skills:

• A big plus if the candidate possesses "any" of the following:
• Proficiency in C++ (OOP)
• Proficiency with Xilinx MPSOC design with writing/debugging with SDKs, BSPs on bare metal/Peta Linux OS.
• Knowledge of PCIe, NVMe, USB protocols.
• Experience with High level synthesis (Xilinx Vivado HLS, AND/OR Mentor Calypto ).

In compliance with pay transparency requirements, the salary range for this role is $111,515 - $151,500. This is not a guarantee of compensation or salary, as final offer amount may vary based on factors including but not limited to experience and geographic location. L3

Harris also offers a variety of benefits, including health and disability insurance, 401(k) match, flexible spending accounts, EAP, education assistance, parental leave, paid time off, and company-paid holidays. The specific programs and options available to an employee may vary depending on date of hire, schedule type, and the applicability of collective bargaining agreements.

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Harris Technologies is proud to be an Equal Opportunity Employer. L3

Harris is committed to treating all employees and applicants for employment with respect and dignity and maintaining a workplace that is free from unlawful discrimination. All applicants will be considered for employment without regard to race, color, religion, age, national origin, ancestry, ethnicity, gender (including pregnancy, childbirth, breastfeeding or other related medical conditions), gender identity, gender expression, sexual orientation, marital status, veteran status, disability, genetic information, citizenship status, characteristic or membership in any other group protected by federal, state or local laws.

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Harris maintains a drug-free workplace and performs pre-employment substance abuse testing and background checks, where permitted by law.